CFET Gate Stack Layout for Higher Density IC Routing
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Solution Overview
Problem
In semiconductor fabrication, achieving better gate density in integrated circuits is challenging due to the need for dummy gate structures in routing, which occupies extra area and complicates the design.
Innovation Solution
The implementation of a complementary field-effect transistor (CFET) with a buried power rail and PMOS/NMOS transistors of different depths, along with an insulating layer to separate gates, allows for reduced cell height and efficient routing without the need for dummy gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If dummy gate structures are added for routing, then routing functionality is achieved, but occupied area increases
Solution Approach 1:
The patent merges the routing function with the gate structure itself by making the gate extend into the source/drain region. This integration eliminates the need for separate dummy gate structures, achieving routing functionality while reducing the occupied area in the active region.
Solution Approach 2:
The patent utilizes the vertical dimension by extending the gate structure downward into the source/drain region rather than adding horizontal extensions. This dimensional change allows routing functionality to be achieved without increasing the planar footprint, thereby reducing occupied area.
2Productivity
If complementary field-effect transistor with different depth PMOS/NMOS is used, then gate density is improved, but device complexity increases
Solution Approach 1:
The patent segments the transistor structure into different depth levels, with PMOS and NMOS transistors positioned at different vertical depths. This segmentation allows independent optimization of each transistor type and enables higher gate density by utilizing the third dimension, while the segmented structure naturally simplifies the control of each transistor type.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the PMOS and NMOS gates that are positioned at different depths. This insulating layer mediates the electrical isolation between the two transistor types, enabling the complex stacked structure to function reliably while maintaining high gate density.
Data Source
AI summary
A method is provided and includes operations below: forming a multilayer stack, wherein the multilayer stack includes multiple first semiconductor layers and multiple second semiconductor layers that are alternately stacked; forming a first source region and a first drain region on opposing sides of a first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack; removing the second semiconductor layers in the multilayer stack; forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack; forming a first insulating layer above the first gate region; and forming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack.