CFET Common Metal Gate Stack With Passivation-Layer Vt Tuning
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in the fabrication process that need to be addressed to maintain device performance and integrity.
Innovation Solution
The formation of complementary field-effect transistors (CFETs) with vertically stacked nanostructure-FETs, utilizing a common metal gate process that integrates a p-type and an n-type nanostructure-FET, and employs a silicon-containing passivation layer to tune threshold voltage without an upper gate etch-back process, enhancing device integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but additional fabrication problems arise that compromise device performance and integrity
Solution Approach 1:
The patent transitions from planar transistor stacking to vertically integrated 3D stacked transistors with complementary p-type and n-type FETs arranged in vertical columns. This dimensional change enables higher integration density while maintaining device performance through careful control of channel materials, gate structures, and interlayer dielectrics in the vertical direction.
Solution Approach 2:
The patent applies different material compositions and structural characteristics to different regions of the vertically stacked transistor structure. Each transistor column has locally optimized channel materials (e.g., SiGe for p-type, Si for n-type), gate dielectric thicknesses, and doping concentrations tailored to the specific performance requirements of that region, allowing high integration density without compromising local device reliability.
2Ease of manufacture
If a dual metal gate process is used with upper gate etch-back, then complementary transistors can be formed, but device damage and performance degradation occur
Solution Approach 1:
Instead of removing the upper gate through etch-back and then forming a new gate structure, the patent inverts the approach by forming the upper gate material in-situ during the same deposition process. The upper gate electrode is formed by depositing metal material that selectively forms on the upper gate dielectric, eliminating the need for destructive etch-back operations and preserving device integrity.
Solution Approach 2:
The patent performs preliminary actions by pre-forming the upper gate dielectric layer and preparing the surface with appropriate adhesion layers before depositing the upper gate metal material. This preliminary preparation ensures that the upper gate forms correctly in-situ without requiring subsequent removal of lower gate structures, avoiding device damage.
3Manufacturing precision
If thick n-type work function material is used, then threshold voltage tuning is achieved, but integration density is reduced
Solution Approach 1:
The patent changes the parameter of work function material thickness by using thin-film deposition techniques to form ultra-thin work function layers (few nanometers thick) instead of thick bulk materials. Threshold voltage tuning is achieved through precise control of deposition thickness and composition rather than relying on thick material layers, thereby maintaining high integration density while preserving manufacturing precision for voltage tuning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies processing, avoids device damage, and increases integration density by forming a common metal gate in one step, eliminating the need for a thick n-type work function material and reducing performance degradation.
Implementation Method 1
forming a silicon-containing passivation layer around the work function material
Data Source
AI summary
A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurality of channel regions.