CFET Gate Trench Etching for Uniform Vertical Dipole Patterning
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Solution Overview
Problem
Existing complementary field-effect transistor (C-FET) structures face challenges in achieving uniform and high-quality performance across varying gate widths and placements due to non-uniform etching rates and unintentional lateral etching during the fabrication process.
Innovation Solution
An etching back process is employed with controlled DC and RF power cycling to ensure even etching gas distribution, forming protective passivation layers on sidewalls and bottoms of gate trenches, allowing for balanced etching rates and uniform recess depths, followed by selective diffusion of dipole dopants into high-k dielectric layers to tune transistor properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for CFET fabrication, then the fabrication process is simple, but the etching rates are non-uniform and lateral etching occurs, leading to poor device performance uniformity
Solution Approach 1:
The patent applies periodic action by cycling between DC and RF power modes during the etching process. The etching process alternates between DC-powered intervals (which provide high ion bombardment energy for vertical etching) and RF-powered intervals (which provide softer, more uniform etching). This periodic switching enables uniform etching rates across varying gate widths while minimizing lateral etching, resolving the contradiction between etching precision and process simplicity.
Solution Approach 2:
The patent changes etching parameters dynamically by switching between DC and RF power modes. During DC-powered intervals, the etching process operates with high ion energy for rapid material removal. During RF-powered intervals, the etching becomes more uniform and controlled. This parameter change strategy enables the process to achieve uniform etching across different gate widths without requiring completely different etching conditions for each case.
2Productivity
If high etching power is used to increase productivity, then etching speed increases, but lateral etching increases and uniformity decreases
Solution Approach 1:
The patent uses periodic action to alternate between high-speed DC etching intervals and uniformity-enhancing RF etching intervals. During DC-powered intervals, the high ion bombardment energy enables rapid material removal, increasing productivity. During RF-powered intervals, the softer plasma conditions restore uniformity and reduce lateral etching. This periodic alternation allows the process to achieve both high etching speed and uniform results, resolving the contradiction between productivity and precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances CFET performance by ensuring uniformity and reliability across different devices, enabling flexible adjustment of transistor properties based on position within the CFET structure, thereby improving device consistency and reliability.
Implementation Method 1
performing an etching process on the dummy material to form a recess exposing a first portion of the barrier layer
Implementation Method 2
doping a dipole dopant into the second high-k dielectric layer
Implementation Method 3
selective diffusion of dipole dopants into high-k dielectric layers
Data Source
AI summary
Method to selectively diffuse dipole dopants into the high-k gate dielectric layer is provided. A method of the present disclosure includes an etching back process controlling DC and bias power, a periodical switching of the bias power is synchronized with a periodical switching of the DC power, leading to a balanced etching rate and uniform depth of recesses in dummy materials within the gate trenches for the subsequent selective diffusion process across different devices. Additionally, during the etching back process, a protective passivation layer can be formed as a barrier on the sidewall of the recess and/or at the bottom of the recess.