CFET Source/Drain Stacking With Ge-Rich Contacts and Isolation
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Solution Overview
Problem
Existing complementary field effect transistors (CFETs) face challenges in increasing transistor density and reducing source/drain contact resistance while maintaining optimal work function and electrical characteristics, particularly due to interference between gate metals and semiconductor nanostructures.
Innovation Solution
The implementation of a CFET structure with an isolation structure between stacked channel regions and the use of pure or high-concentration germanium for source/drain regions, along with a gate all around transistor design, to enhance electrical characteristics and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate metals are placed adjacent to semiconductor nanostructures to form CFETs, then transistor density increases, but gate metal interference with semiconductor nanostructures occurs affecting work function and electrical characteristics
Solution Approach 1:
A dielectric isolation structure is introduced as an intermediary between the gate metal and semiconductor nanostructures. This isolation structure prevents direct contact and interference between the gate metal and semiconductor channels, thereby maintaining optimal work function and electrical characteristics while still enabling high transistor density through the CFET architecture.
Solution Approach 2:
The CFET structure is segmented into distinct regions: gate metal regions, semiconductor channel regions, and dielectric isolation regions. This segmentation allows the gate metal to be positioned adjacent to semiconductor nanostructures for high density while the dielectric segments prevent harmful interactions, resolving the contradiction between density and electrical performance.
2Ease of manufacture
If conventional source/drain structures are used in CFETs, then manufacturing is simplified, but source/drain contact resistance remains high
Solution Approach 1:
The material composition parameter of the source/drain regions is changed by incorporating high-concentration germanium (e.g., SiGe with >50% Ge or pure Ge). This parameter change reduces the bandgap and improves carrier mobility, thereby reducing source/drain contact resistance while maintaining compatibility with existing manufacturing processes.
Solution Approach 2:
The source/drain regions are formed using composite semiconductor materials (SiGe alloys or Ge-Si combinations) that combine the advantages of silicon (compatibility with existing processes) and germanium (high mobility, low contact resistance). This composite approach reduces contact resistance while maintaining ease of manufacture through established epitaxial growth techniques.
Data Source
AI summary
A device and associated method that includes a plurality of first nanostructures formed in a first stack. The device also includes a plurality of second nanostructures formed in a second stack. The device also includes a first source/drain structure adjacent to the plurality of first nanostructures, the first source/drain structure including a first semiconductor having silicon and germanium. The device also includes a second source/drain structure stacked vertically over the first source/drain structure and adjacent to the plurality of second nanostructures, the second source/drain structure having a second semiconductor in which the germanium concentration exceeds the germanium concentration of the first semiconductor.