CFET Inner Spacer Layout for Junction Overlap and Capacitance
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Solution Overview
Problem
Existing complementary metal-oxide-semiconductor field effect transistors (CMOSFETs) face challenges in achieving optimal performance due to uniform inner spacers for both p-type and n-type FETs, leading to suboptimal DC performance and parasitic capacitance.
Innovation Solution
A novel structure and fabrication method that allows for varying inner spacer thickness and width for p-type and n-type FETs within a CFET, optimizing individual performance parameters such as junction overlap, parasitic capacitance, and Drain-induced barrier lowering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform inner spacers are used for both p-type and n-type FETs, then manufacturing process is simplified, but DC performance and parasitic capacitance are suboptimal
Solution Approach 1:
The patent applies local quality by providing different inner spacer thicknesses for p-type and n-type FETs. Specifically, the n-type FET has a first inner spacer thickness while the p-type FET has a second inner spacer thickness that is greater than the first. This allows each transistor type to have optimized electrical characteristics (DC performance and parasitic capacitance) tailored to its specific requirements, rather than using a uniform spacer design for both types.
2Device complexity
If uniform inner spacers are used for both p-type and n-type FETs, then device structure is simplified, but parasitic capacitance is not optimized
Solution Approach 1:
The patent implements local quality by varying the inner spacer thickness according to the specific FET type. The n-type FET utilizes a thinner first inner spacer to minimize parasitic capacitance, while the p-type FET employs a thicker second inner spacer to achieve optimal electrical performance. This localized differentiation reduces harmful parasitic effects without requiring complex overall device architecture.
3Ease of manufacture
If uniform inner spacers are used for both p-type and n-type FETs, then fabrication process is simplified, but junction overlap is suboptimal
Solution Approach 1:
The patent applies local quality by configuring different inner spacer thicknesses to achieve optimal junction overlap for each FET type. The thinner first inner spacer in the n-type FET enables precise junction overlap control, while the thicker second inner spacer in the p-type FET provides similar optimization. This approach maintains good manufacturing precision without significantly complicating the fabrication process.
Data Source
AI summary
A method of forming a semiconductor structure includes forming a fin structure including first and second semiconductor layers alternately stacked; forming source/drain trenches in the fin structure; recessing the first semiconductor layers to form inner spacer recesses; and forming first, second, and third inner spacers in the inner spacer recesses. The second inner spacers are vertically sandwiched between the first and third inner spacers. The method further includes recessing the first inner spacers and first portions of the second inner spacers to form recessed first inner spacers and recessed first portions of the second inner spacers; and forming first and second source/drain features in the source/drain trenches. The first source/drain features contact the recessed first inner spacers and the recessed first portions of the second inner spacers. The second source/drain features contact the third inner spacers and second portions of the second inner spacers.