CFET Dual Inner Spacer Structure for Independent Gate-Length Tuning
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down transistor dimensions while maintaining control over inner spacer formation in complementary FET (CFET) devices, particularly as gate pitches become smaller than 50 nm, leading to difficulties in achieving precise control over inner spacer formation and independent tuning of effective gate lengths for top and bottom devices.
Innovation Solution
A dual inner spacer module for monolithic CFET is proposed, allowing independent tuning of the cavity recess for the top and bottom devices, which improves the control over inner spacer formation and enables independent adjustment of the effective gate length for each device, enhancing the scalability and performance of nanosheet architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single inner spacer formation is used, then manufacturing process is simpler, but control over inner spacer formation deteriorates when gate pitch is smaller than 50 nm
Solution Approach 1:
The single inner spacer formation process is segmented into two independent inner spacer formation processes, allowing separate control of first and second inner spacers. This segmentation enables precise control of each spacer's dimensions and positioning, resolving the control deterioration issue when gate pitch is smaller than 50 nm.
Solution Approach 2:
The first inner spacer is formed in advance before the second inner spacer formation. This preliminary action allows the first inner spacer to serve as a foundation for subsequent processing, enabling independent tuning of effective gate lengths while maintaining process efficiency.
2Productivity
If conventional CFET structure is used, then chip area is larger, but device density decreases
Solution Approach 1:
The invention transitions from planar device arrangement to vertical stacking, with first and second FET devices stacked in vertical direction. This dimensional change doubles the device density without increasing chip area, as both devices share the same footprint area through vertical integration.
Solution Approach 2:
The first and second FET devices are nested vertically within the same lateral footprint area. The first FET device is positioned at a first level while the second FET device is positioned at a second level, creating a nested configuration that maximizes space utilization and increases device density.
3Adaptability or versatility
If independent inner spacer formation is implemented, then effective gate length tuning is improved, but manufacturing process complexity increases
Solution Approach 1:
Different inner spacers (first and second inner spacers) are formed with different local qualities, including different materials, dimensions, and positioning. This local differentiation enables independent tuning of effective gate lengths for top and bottom FET devices, allowing optimization of each device's performance characteristics.
Solution Approach 2:
The invention changes multiple parameters including inner spacer material composition, thickness, width, and positioning to achieve independent effective gate length tuning. By varying these parameters for first and second inner spacers differently, the effective gate lengths of top and bottom FET devices can be independently optimized.
Data Source
AI summary
A method of forming a semiconductor structure is provided. A complementary FET (CFET) device including a first FET device and a second FET device isolated with each other by a middle dielectric layer is formed. The first and second FET devices are stacked over each other in a vertical direction. A first inner spacer is formed immediately below and above a peripheral portion of each of a plurality of first nanosheet channels of the first FET device. A second inner spacer is formed immediately below and above a peripheral portion of each of a plurality of second nanosheet channels of the second FET device. The first inner spacers and the second inner spacers are formed at different process steps.