CFET Local Interconnect Epitaxy for High-Aspect-Ratio Contacts
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Solution Overview
Problem
The formation of contact plugs in Complementary Field-Effect Transistors (CFETs) with high aspect ratios poses challenges due to the difficulty in electrically connecting overlapping transistors, particularly in forming local interconnections.
Innovation Solution
A selective epitaxy process is employed to form a semiconductor layer on the lower source/drain region, reducing the aspect ratio of the opening for the contact plug, and forming a contact plug that electrically connects the lower and upper source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are formed to electrically connect overlapping transistors in CFETs, then electrical connectivity between transistors is achieved, but the high aspect ratio of the contact plugs makes formation difficult
Solution Approach 1:
The patent applies preliminary action by forming a semiconductor layer in the lower source/drain region before forming the contact plug. This pre-formed layer serves as a foundation that reduces the aspect ratio of the opening, making subsequent contact plug formation easier while ensuring reliable electrical connectivity between overlapping transistors
2Ease of manufacture
If the aspect ratio of the opening is reduced by forming a semiconductor layer, then contact plug formation becomes easier, but an additional epitaxy step is required
Solution Approach 1:
The patent applies local quality by forming the semiconductor layer selectively only in the lower source/drain region where it is needed to reduce the aspect ratio. The selective epitaxy process targets specific areas rather than uniformly treating the entire structure, adding the necessary complexity only where required for successful contact plug formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process effectively reduces the aspect ratio of the opening, making it easier to form a reliable local interconnect without voids, thereby improving the electrical connectivity between transistors.
Implementation Method 1
A selective epitaxy process is employed to form a semiconductor layer on the lower source/drain region, reducing the aspect ratio of the opening for the contact plug
Data Source
AI summary
A method includes forming Complementary Field-Effect Transistors including a lower transistor comprising a lower source/drain region, and an upper transistor including an upper source/drain region. An upper dielectric layer over the upper source/drain region and a lower dielectric layer under the upper source/drain region are etched to form an opening. A sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening. An epitaxy process is performed to form a first semiconductor layer on the sidewall of the upper source/drain region, and a second semiconductor layer on the top surface of the lower source/drain region. The first semiconductor layer is then removed, a contact plug is formed in the opening to electrically connects the upper source/drain region to the second semiconductor layer and the lower source/drain region.