CFET Through-Substrate Interconnect Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge in integrated circuits is to reduce parasitic capacitance caused by large conductive through-substrate layers (TSL) in 3D stacked complementary field-effect transistors (CFETs), which degrades performance and power efficiency due to gate-to-source/drain capacitances, and wastes metal routing resources.
Innovation Solution
Incorporating an L-shaped conductive TSL with a cutout region filled with dielectric material to reduce parasitic capacitance and enhance routing flexibility, allowing contact landing on dielectric material without shorting to the conductive TSL, and using a low-k dielectric for gate isolation to control resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large conductive through-substrate layer (TSL) is used in 3D stacked CFETs, then electrical connectivity between stacked transistors is achieved, but parasitic capacitance increases causing performance degradation and power efficiency loss
Solution Approach 1:
The conductive TSL is segmented into multiple separate conductive regions rather than a single large continuous layer. Each conductive region is positioned to contact specific source/drain regions of stacked transistors, dividing the original large capacitive structure into smaller discrete capacitive elements, thereby reducing total parasitic capacitance while maintaining necessary electrical connectivity
Solution Approach 2:
Different regions of the TSL are given different properties: conductive regions provide electrical connectivity where needed, while dielectric regions provide isolation to reduce parasitic capacitance. The TSL structure transitions from uniform conductivity to spatially varying electrical properties, with conductive material placed only where electrical connection is required and dielectric material placed where isolation is needed
2Productivity
If a large conductive TSL is used, then transistor stacking is enabled, but metal routing resources are wasted
Solution Approach 1:
Conductive material is extracted from regions where it is not needed for electrical connectivity. By removing excess conductive material and replacing it with dielectric material, the TSL structure uses metal routing resources only where functionally necessary, freeing up other areas for additional routing or device structures
Solution Approach 2:
The TSL structure utilizes the vertical dimension to provide electrical connectivity between stacked transistors through the substrate, rather than relying solely on lateral metal routing. This vertical conduction path eliminates the need for additional horizontal metal layers, conserving metal routing resources for other circuit functions
3Reliability
If contacts land on conductive TSL, then electrical connection is established, but short circuits occur
Solution Approach 1:
Dielectric material serves as an intermediary between contacts and the conductive TSL in regions where electrical isolation is needed. The dielectric layer prevents direct contact between conductive elements that would otherwise create short circuits, while still allowing the conductive TSL regions to provide necessary electrical connections where not blocked
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves electrical characteristics of CFETs by reducing parasitic capacitance, enhancing routing flexibility, and preventing short circuits, leading to better performance and increased wafer yields.
Implementation Method 1
reduce parasitic capacitance caused by large conductive through-substrate layers (TSL) in 3D stacked complementary field-effect transistors (CFETs)
Data Source
AI summary
A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact. The interconnect structure includes: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being in the gate isolation structure; an opening in the conductive layer, the opening overlapping the fourth source/drain region, the second source/drain region or both; and a dielectric layer in the opening and on the conductive layer in the gate isolation structure.