CFET Interconnect Structure for Low-Resistance Vertical Routing
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Solution Overview
Problem
The process of manufacturing deep vias in complementary field-effect transistors (CFETs) is challenging due to their high aspect ratio, leading to high resistance and complexity, which affects the performance and efficiency of the CFETs.
Innovation Solution
The use of an interconnect structure with a non-tapered design that facilitates signal transmission in the Z-direction, reducing resistance and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a deep via is used to vertically connect n-type and p-type devices in CFET, then vertical connection is achieved, but the high aspect ratio leads to high resistance and manufacturing challenges
Solution Approach 1:
The patent transitions from vertical deep via connections to horizontal interconnect structures at multiple stacked levels. Instead of drilling deep vertical holes through the substrate, the design uses multiple conductive layers arranged in three-dimensional space, changing the connection dimension from purely vertical to a combination of horizontal and vertical routing through stacking.
Solution Approach 2:
The patent implements nested interconnect structures where multiple conductive layers are stacked within each other, with lower-level interconnects embedded in substrate and upper-level interconnects formed above them. This nested arrangement allows multiple connection paths to be integrated in a compact vertical footprint, reducing the need for deep individual vias.
2Reliability
If a deep via with high aspect ratio is used, then vertical connection is achieved, but resistance increases
Solution Approach 1:
The patent reduces resistance by changing from long vertical via paths to shorter horizontal interconnect paths at multiple stacked levels. The connection is achieved through a combination of horizontal routing in conductive layers and vertical transitions at endpoints, significantly reducing the total path length and associated resistance compared to deep vertical vias.
Solution Approach 2:
The patent merges multiple connection functions into integrated interconnect structures that combine horizontal and vertical routing capabilities. The stacked conductive layers with via connections at endpoints create unified transmission paths that achieve vertical connectivity while minimizing resistance through optimized current flow paths.
3Reliability
If deep via process is used for CFET manufacturing, then vertical connection is achieved, but process complexity increases
Solution Approach 1:
The patent simplifies manufacturing by replacing complex deep via drilling and filling processes with standard planar photolithography and deposition processes used for forming conductive layers. The vertical connection is achieved through stacked horizontal layers rather than deep vertical structures, utilizing existing fabrication capabilities.
Solution Approach 2:
The patent segments the vertical connection function into multiple horizontal interconnect layers stacked at different levels. Each layer can be fabricated independently using standard processes, and the segments are connected through localized via structures at endpoints, dividing the complex deep via fabrication into simpler, modular steps.
Data Source
AI summary
An integrated circuit is provided, including a first cell. The first cell includes a first pair of active regions, at least one first gate, two first conductive segments, and a first interconnect structure. The first pair of active regions extends in a first direction and stacked on each other. The at least one first gate extends in a second direction different from the first direction, and is arranged across the first pair of active regions, to form at least one first pair of devices that are stacked on each other. The first conductive segments are coupled to the first pair of active regions respectively. The first interconnect structure is coupled to at least one of a first via or one of the two first conductive segments.