CFET Dielectric Isolation Fill for High-Aspect Ratio Gate Canyons
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Solution Overview
Problem
Current process methods fail to fill the high-aspect canyon between stacked NMOS and PMOS devices in CFET architecture without voids or seams, impacting wafer die yield.
Innovation Solution
A method involving repetitive deposition and etching of dielectric material, such as SiO2, SiN, SiON, SiOCN, or SiCN, using atomic layer deposition (ALD) and reactive ion etching (RIE) to fill the voids between complementary metal-oxide-semiconductor (MOS) devices, with optional sidewall poisoning to inhibit adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current process methods are used to fill the gate canyon, then the filling process is simpler, but voids and seams are formed in the NP dielectric isolation
Solution Approach 1:
The filling process is divided into multiple sequential stages: initial fill to a first height, removal of excess material, and subsequent fill to final height. This segmentation allows each stage to be optimized independently, ensuring void-free filling in the high-aspect-ratio canyon while managing process complexity through systematic breakdown of the overall task.
Solution Approach 2:
The method employs periodic cycles of deposition and removal operations. Material is deposited to a specific height, then excess is removed, followed by another deposition cycle to reach the final height. This periodic action ensures complete filling without voids while maintaining control over the complex process through repeated, manageable steps.
2Reliability
If the NP dielectric isolation fill is not void-free, then downstream wet processes are compromised, but achieving void-free fill with current methods is impossible
Solution Approach 1:
The method performs preliminary filling to a first height before attempting the final fill. This preliminary action prepares the cavity by establishing a foundation layer, ensuring that the subsequent final fill can proceed without forming voids or seams. The preliminary fill quality directly enables the reliability of downstream wet processes.
Solution Approach 2:
The invention replaces conventional single-step mechanical filling with a multi-step deposition process that uses controlled material accumulation. By substituting the simple fill operation with sequential deposition and removal cycles, the method achieves superior fill quality (void-free) that directly improves wafer die yield and reliability.
3Productivity
If the canyon is filled before the cavity, then the process is faster, but the NP dielectric isolation cannot be properly formed
Solution Approach 1:
The filling operation is segmented into distinct phases: first filling the canyon region, then filling the NP dielectric isolation cavity. This segmentation ensures that each region receives appropriate filling treatment in the correct sequence, maintaining isolation formation quality while optimizing overall productivity through efficient staged processing.
Solution Approach 2:
The canyon filling is performed as a preliminary action before the NP dielectric isolation cavity filling. This preliminary fill prepares the structure by establishing the canyon region, enabling subsequent proper formation of the NP dielectric isolation without compromising isolation quality, while maintaining productive throughput through sequential operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures seamless filling of the voids between MOS devices, preventing downstream wet process issues and enhancing wafer die yield.
Implementation Method 1
depositing and etching steps to fill the void between the first MOS device and the second MOS device of the first CFET device
Implementation Method 2
etching the dielectric material
Data Source
AI summary
A system and method for forming an isolator in a complementary field effect transistor (CFET) is disclosed. In one aspect the method includes: fabricating a plurality of CFET devices, each device including a first metal-oxide-semiconductor (MOS) device and a second MOS device, wherein the first MOS device and the second MOS device are complementary; removing a filler between the first MOS device and the second MOS device of a first CFET device; depositing a dielectric material between the first CFET device and a second CFET device to fill a void between the first MOS device and the second MOS device of the first CFET device; etching the dielectric material; repeating the depositing and etching steps to fill the void between the first MOS device and the second MOS device of the first CFET device; and performing a final etching to remove the dielectric material between the first and second CFET.