CFET Channel-Length Layout for Isolation and Low Crosstalk
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Solution Overview
Problem
Existing complementary field-effect transistors (CFETs) face challenges in effectively isolating N-type and P-type GAAFETs, leading to signal crosstalk, which hampers performance and density in semiconductor devices.
Innovation Solution
A semiconductor device design featuring a CFET structure with a first transistor and a second transistor stacked vertically, where the first transistor has a longer channel length than the second, and a common gate structure wrapping around both, with dielectric layers and spacers to isolate and separate the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If N-type and P-type GAAFETs are stacked vertically to increase device density, then on-chip device density is improved, but signal crosstalk increases due to insufficient isolation
Solution Approach 1:
A dielectric layer is introduced as an intermediary substance between the N-type and P-type GAAFETs in the vertical stack. This dielectric layer acts as a mediator that electrically isolates the two transistor types, preventing signal crosstalk while allowing the vertical stacking architecture to maintain high device density.
Solution Approach 2:
The gate structure is segmented into a first portion wrapping the N-type GAAFET and a second portion wrapping the P-type GAAFET. This segmentation allows independent control and isolation of each transistor type, reducing electromagnetic interference and signal crosstalk between the vertically stacked devices.
2Reliability
If channel lengths are differentiated between N-type and P-type transistors to optimize performance, then transistor performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different channel lengths to N-type and P-type GAAFETs based on their specific performance requirements. The first channel length is optimized for N-type transistor characteristics while the second channel length is optimized for P-type transistor characteristics, allowing each transistor type to operate at its optimal performance point.
3Area of stationary object
If gate structure wraps around both N-type and P-type nanostructures to reduce area, then area consumption is reduced, but device complexity increases
Solution Approach 1:
The gate structure extends in the vertical dimension to wrap around both N-type and P-type GAAFETs that are stacked vertically. This three-dimensional gate configuration reduces the lateral area footprint of the transistor pair while the dielectric layer and gate segmentation manage the increased structural complexity.
Data Source
AI summary
A semiconductor device includes a plurality of first nanostructures extending along a first lateral direction with a first length, and spaced from one another along a vertical direction. The semiconductor device includes a plurality of second nanostructures extending along the first lateral direction with a second length, and spaced from one another along the vertical direction. The semiconductor device includes a dielectric layer interposed between the plurality of first nanostructures and the plurality of second nanostructures along the vertical direction. The second length is different from the first length.