Hybrid Nanostructure CFET Isolation for Gate Work Function Control
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Solution Overview
Problem
Forming gate electrodes in stacked complementary field effect transistors (CFETs) with desired characteristics is challenging, leading to improper functioning of one or both transistors, and there is a risk of interference between gate metals affecting the threshold voltage of the transistors.
Innovation Solution
Incorporating an isolation structure between the semiconductor nanostructures of stacked transistors in a CFET, which separates the channel regions and prevents interference from the gate metal of one transistor affecting the other, thereby maintaining desired work functions and reducing gate-to-drain capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate electrodes are formed in stacked transistors without isolation structures, then manufacturing process is simpler, but gate metal from one transistor interferes with the other transistor's work function
Solution Approach 1:
An isolation structure is introduced as an intermediary element between the stacked transistors. This isolation structure physically separates the gate metals of the N-type and P-type transistors, preventing electrical interference and work function coupling while allowing both transistors to function independently with their respective gate electrodes.
2Object-affected harmful factors
If isolation structure is added between stacked transistors, then gate metal interference is prevented, but device complexity increases
Solution Approach 1:
The isolation structure serves as a mediator that prevents harmful electrical interactions between stacked transistors. By placing this intermediate layer between the channel regions, the patent eliminates work function interference without requiring complex modifications to the transistor designs themselves.
3Productivity
If gate electrodes are formed in stacked transistors, then transistor density is increased, but manufacturing precision requirements become more difficult to meet
Solution Approach 1:
The isolation structure acts as a protective barrier that maintains manufacturing precision by preventing cross-contamination and electrical interference between adjacent gate electrodes. This allows the high-density stacked configuration to be manufactured with controlled precision without the gate metals of different transistors affecting each other's electrical characteristics.
Data Source
AI summary
An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor having a first semiconductor nanostructure corresponding to a channel region of the first semiconductor nanostructure and a first gate metal surrounding the second semiconductor nanostructure. The CFET includes a transistor including a second semiconductor nanostructure above the first semiconductor nanostructure and a second gate metal surrounding the second semiconductor nanostructure. The CFET includes an isolation structure between the first and second semiconductor nanostructures.