CFET Layer-Transfer Structure for Higher Fin Density and Current
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Solution Overview
Problem
The fabrication of CFET devices is limited by the height/width ratio of fins, which restricts the density of transistors per unit area while maintaining acceptable electrical performance.
Innovation Solution
A process involving a double semiconductor-on-insulator substrate is developed, where two single-crystal semiconductor layers and electrically insulating layers are transferred onto a carrier substrate, allowing for precise control of channel height and separation, and the use of different materials and doping types to optimize transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of fins is decreased to increase transistor density, then the density of transistors per unit area is improved, but the electrical current capacity deteriorates due to insufficient channel height
Solution Approach 1:
The patent transitions from planar FinFET architecture to vertically stacked CFET architecture, moving the transistor channels from a two-dimensional lateral arrangement to a three-dimensional vertical stacking configuration. This dimensional change allows multiple transistor channels to occupy the same footprint area, dramatically increasing transistor density while maintaining adequate channel height for electrical current capacity through the vertical stacking of n-type and p-type FinFETs
Solution Approach 2:
The patent implements nested structures by placing one FinFET channel inside another in the vertical dimension, with the first FinFET channel (n-type or p-type) positioned below the second FinFET channel (opposite type). This nesting arrangement allows both channels to share the same lateral footprint while maintaining independent electrical pathways, effectively doubling the current capacity within the same area without compromising either channel's height
2Reliability
If the height/width ratio of fins is increased to maintain electrical performance, then the electrical current capacity is improved, but the transistor density deteriorates
Solution Approach 1:
Instead of increasing the height/width ratio of individual fins to maintain current capacity, the patent utilizes the vertical dimension by stacking multiple FinFET channels one above another. This approach maintains a moderate height/width ratio for each individual fin while achieving superior current capacity through the cumulative effect of multiple channels in series, thereby preserving high transistor density
3Ease of manufacture
If conventional sacrificial layer etching is used to separate n-type and p-type FinFETs, then the manufacturing process is simplified, but the precision and uniformity of channel thickness deteriorates
Solution Approach 1:
The patent extracts and removes the conventional sacrificial layer etching step from the manufacturing process. Instead of using a sacrificial layer that requires selective etching to separate n-type and p-type FinFETs, the invention directly forms both channels through a unified process that eliminates the need for sacrificial material deposition, patterning, and removal steps, thereby simplifying manufacturing while achieving precise channel thickness control through direct epitaxial growth
Solution Approach 2:
The patent replaces the mechanical/chemical sacrificial layer removal process with a direct selective epitaxial growth approach. Instead of using mechanical etching to define channels after sacrificial layer removal, the invention uses controlled chemical vapor deposition to directly grow silicon layers with precise thickness control, substituting a multi-step mechanical process with a more precise chemical deposition process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision and uniformity of channel thickness, increases the height of transistors, and improves electrical performance by allowing for a higher density of transistors without compromising electrical current capacity.
Implementation Method 1
a heat treatment at a sufficiently high temperature to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS
Data Source
AI summary
A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.