CFET Memory Cell Bit-Line Layout With Dual-Side Data Paths
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Solution Overview
Problem
Existing CFET structures for memory cells face issues with increased parasitic resistance and capacitance due to one-sided data lines, which negatively impact performance as the scaling trend narrows metal width and spacing.
Innovation Solution
The memory cell design incorporates dual-side data lines formed by bit lines on both sides of the substrate, utilizing multiple metal tracks connected through vertical contact structures and epitaxial structures, reducing parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If one-sided data lines are used in CFET structures, then device complexity is reduced, but parasitic resistance increases
Solution Approach 1:
The patent transitions from a planar one-sided data line configuration to a three-dimensional dual-side configuration by extending bit lines to both front and back surfaces of the substrate. This dimensional change allows data lines to be routed on both sides of the memory cell, effectively doubling the conductive paths and reducing parasitic resistance without increasing planar device complexity
Solution Approach 2:
The data line system is segmented into front-side bit lines and back-side bit lines that are electrically connected through vertical contacts. This segmentation allows each side to be independently optimized and connected through multiple parallel paths, reducing the overall parasitic resistance of the data line system
2Productivity
If metal width and spacing are narrowed for scaling, then integration density increases, but parasitic resistance increases
Solution Approach 1:
The patent utilizes the third dimension (substrate thickness) by routing bit lines on both front and back surfaces and connecting them through vertical contacts. This allows the horizontal metal dimensions to be scaled down for higher density while the vertical dimension provides additional parallel conduction paths that compensate for the increased resistance from narrower metals
Solution Approach 2:
The patent merges front-side and back-side bit line systems into a unified dual-side data line architecture. This combination creates multiple parallel conduction paths that reduce overall parasitic resistance, allowing individual metal tracks to be narrower while maintaining low resistance through the parallel path effect
Data Source
AI summary
A memory device includes a substrate having a first side and a second side; a first transistor, a second transistor, a third transistor, and a fourth transistor formed on the first side, the first to fourth transistors each formed with a p-type conductivity; a fifth transistor and a sixth transistor formed on the first side and over the first to fourth transistors, the fifth to sixth transistors each formed with an n-type conductivity; a first interconnect structure formed on the first side and over the fifth to sixth transistors, and coupled to the first transistor, wherein the first interconnect structure is configured as a portion of a first bit line; and a second interconnect structure formed on the second side, and also coupled to the first transistor, wherein the second interconnect structure is configured as another portion of the first bit line.