CFET Memory Cell Access Structure for Set/Reset Voltage Balance
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Solution Overview
Problem
Modern integrated circuits face challenges in optimizing both set and reset operations of non-volatile memory due to the limitations of using N-type field effect transistors (NFETs), while volatile memory, such as SRAM, requires large chip areas due to the deployment of NFETs and P-type field effect transistors (PFETs on the same plane.
Innovation Solution
The use of complementary field effect transistors (CFETs) with vertically stacked NFETs and PFETs as access transistors in non-volatile memory cells and SRAM cells, minimizing footprint area and enabling efficient set and reset operations without increasing power supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NFET is used as access transistor in non-volatile memory, then strong logic low voltage transmission is achieved, but weak logic high voltage transmission prevents optimization of both set and reset operations
Solution Approach 1:
The patent combines NFET and PFET into a single vertically stacked CFET structure where both transistor types work together as a unified access transistor. This merging allows the device to simultaneously provide strong logic low voltage transmission (via NFET) and strong logic high voltage transmission (via PFET), enabling optimization of both set and reset operations in non-volatile memory.
Solution Approach 2:
The patent transitions from lateral placement of NFET and PFET on the same plane to vertical stacking in the third dimension. This dimensional change allows both transistor types to be integrated within a compact footprint while maintaining their complementary functions, resolving the voltage transmission limitations of single-transistor designs.
2Ease of operation
If NFETs and PFETs are deployed on the same plane in SRAM cells, then access transistor functionality is achieved, but large chip area is required
Solution Approach 1:
The patent stacks NFET and PFET vertically in the third dimension rather than placing them laterally on the same plane. This vertical integration reduces the horizontal footprint of each SRAM cell significantly, enabling higher density memory arrays while maintaining full access transistor functionality through the complementary transistor pair.
Solution Approach 2:
The patent nests the PFET structure within the same lateral footprint as the NFET structure by stacking them vertically. The PFET is positioned above the NFET with shared source/drain regions, creating a compact nested configuration that minimizes the overall area required for each access transistor.
3Productivity
If feature size of NFETs and PFETs is reduced to increase density, then integration density improves, but manufacturing complexity and difficulty increase
Solution Approach 1:
By moving to vertical stacking, the patent achieves higher integration density without proportionally reducing lateral feature sizes. The vertical dimension provides additional scaling space, allowing manufacturers to increase density by stacking more layers rather than continuously shrinking already-difficult-to-manufacture lateral features.
Solution Approach 2:
The patent segments the transistor structure into distinct vertical layers (NFET at bottom, PFET at top) with intermediate dielectric layers. This segmentation into manageable layers simplifies the manufacturing process compared to attempting to create increasingly smaller lateral features, as each layer can be formed using standard thin-film deposition and patterning techniques.
Data Source
AI summary
A memory device and a semiconductor die are provided. The memory device includes: a non-volatile storage device, with a first terminal coupled to a bit line; and an access transistor, configured to control electrical connection between a second terminal of the non-volatile storage device and a source line, and comprising an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) stacked on the NFET. A common source/drain terminal of the NFET and the PFET is coupled to the second terminal of the non-volatile storage device. Another common source/drain terminal of the NFET and the PFET is coupled to the source line. Further, gate terminals of the NFET and the PFET are coupled to different word lines.