Stacked C-FET Memory Cell Structure for Asymmetric Channel Widths
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Solution Overview
Problem
The vertical stacked structure of complementary field effect transistors (C-FETs) in semiconductor technology limits the optimization of write margin, noise margin, alpha ratio, and beta ratio in memory cells, as both p-type and n-type FETs have the same dimensions, restricting the improvement of functional density and performance in integrated circuits.
Innovation Solution
The introduction of pass-gate transistors with a greater channel width compared to pull-up/pull-down transistors in memory cells, allowing for improved Vt tuning and mobility tuning, which enhances memory operations by reducing leakage current and optimizing resistance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical stacked C-FET structure is used to increase device density, then functional density is improved, but the ability to optimize write margin, noise margin, alpha ratio, and beta ratio is limited due to identical dimensions of p-type and n-type FETs
Solution Approach 1:
The patent segments the transistor dimensions by introducing different channel width options for p-type and n-type FETs within the stacked structure. This allows independent optimization of each transistor type's dimensions to achieve desired write margin, noise margin, alpha ratio, and beta ratio characteristics while maintaining the high-density vertical stacked architecture.
Solution Approach 2:
The patent applies local quality by allowing different channel width dimensions specifically for p-type and n-type FETs in certain stacked configurations, while other dimensions remain uniform. This localized dimensional differentiation enables optimization of electrical characteristics without compromising the overall compact stacked structure.
2Ease of manufacture
If identical dimensions are used for p-type and n-type FETs in stacked structure, then manufacturing simplicity is maintained, but performance optimization is restricted
Solution Approach 1:
The patent maintains manufacturing simplicity by keeping most dimensions uniform across p-type and n-type FETs, while introducing dimensional differences only where specifically needed for performance optimization. This selective approach minimizes fabrication complexity while achieving the required performance characteristics.
Solution Approach 2:
The patent changes specific dimensional parameters (channel width) for p-type and n-type FETs in certain stacked configurations to optimize performance. This parameter differentiation is applied selectively to achieve desired electrical characteristics without fundamentally changing the manufacturing process.
Data Source
AI summary
A method includes forming a first bottom-tier transistor; forming a second bottom-tier transistor, the first and second bottom-tier transistors sharing a same source/drain region; forming a first top-tier transistor over the first bottom-tier transistor, the first top-tier transistor comprising a first channel layer and a first gate structure around the first channel layer; forming a second top-tier transistor over the second bottom-tier transistor, the second top-tier transistor comprising a second channel layer and a second gate structure around the second channel layer, the first and second top-tier transistors sharing a same source/drain region, wherein from a top view, a first dimension of the first channel layer in a lengthwise direction of the first gate structure is different than a second dimension of the second channel layer in the lengthwise direction of the first gate structure.