Work Function Metal Patterning in Nanosheet CFETs With Sacrificial Spacing
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Solution Overview
Problem
The fabrication of stacked nanosheet complementary field effect transistors (CFETs) is challenging due to difficulties in selectively masking the devices, leading to incomplete mask filling and potential damage to lower devices during processing of the upper device, which affects device yield and power efficiency.
Innovation Solution
The use of a sacrificial layer between the upper and lower device regions creates a greater distance, allowing complete masking of the lower device during processing, and the formation of work function metal layers that do not exceed the dielectric spacer layer, ensuring precise patterning and structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked CFETs are formed without a sacrificial layer, then device density is improved, but masking completeness deteriorates and lower devices are damaged during upper device processing
Solution Approach 1:
A sacrificial layer is introduced as an intermediary element between the upper and lower device regions. This layer enables complete masking of the lower device during upper device processing by providing additional vertical separation, preventing mask material from bridging between devices. After processing, the sacrificial layer is removed to achieve the final high-density stacked structure.
2Ease of manufacture
If work function metal layers extend above the dielectric spacer layer, then fabrication simplicity is improved, but patterning precision deteriorates
Solution Approach 1:
The work function metal layers are formed with controlled heights that do not extend above the dielectric spacer layer in a preliminary formation step. This preliminary height control enables precise subsequent patterning operations. The metal layers are later extended to final heights after patterning is complete, achieving both precision and simplicity.
3Adaptability or versatility
If stacked CFETs are formed with different FET structures, then device functionality is improved, but structural stability deteriorates
Solution Approach 1:
Different FET structures (n-type and p-type) are implemented in different vertical regions of the stacked device. The lower device region contains one FET structure type while the upper device region contains another, allowing each region to be optimized for its specific function. The dielectric spacer layer provides a stable interface between these different structures.
Data Source
AI summary
Semiconductor devices, and methods of forming the same, include forming a stack of channel layers, including an upper device region and a lower device region. The upper device region is separated from the lower device region by a dielectric spacer layer. A first work function metal layer is formed on the channel layers in the lower device region. A height of the first work function metal layer does not rise above the dielectric spacer layer. A second work function metal layer is formed on the channel layers in the upper device region.