CFET Nanosheet Layout for Balanced N/P Drive Current
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Solution Overview
Problem
Conventional complementary field effect transistors (CFETs) face challenges in achieving balanced n and p drive currents due to disparities in carrier mobility and gate dimensions, leading to imbalanced drive currents and temperature instability.
Innovation Solution
The design involves an n-channel field effect transistor (nFET) with horizontal p-doped nanosheet channels in a first vertical stack and a p-channel field effect transistor (pFET) with horizontal n-doped nanosheet channels in a second vertical stack, where the ratio of channel widths to lengths is adjusted to equalize the saturation currents of both transistors, using a gate-all-around (GAA) structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional transistor scaling is continued, then device miniaturization is achieved, but drive current imbalance between nFET and pFET worsens
Solution Approach 1:
The patent applies local quality by creating different channel structures for nFET and pFET within the same CFET device. The n-channel region has a first channel structure with specific dimensions while the p-channel region has a second channel structure with different dimensions, allowing each transistor type to have optimized local characteristics that compensate for the inherent mobility differences between electrons and holes, thereby achieving balanced drive currents despite continued scaling
Solution Approach 2:
The patent changes critical geometric parameters including channel width (W1, W2), channel length (L1, L2), and vertical separation distance (D1, D2) between the nFET and pFET channels. By carefully selecting different parameter sets for each transistor type and optimizing the ratio W/L for each, the invention compensates for mobility disparities and achieves balanced saturation currents while maintaining scaled-down dimensions
2Length of moving object
If CFET structure is used to improve scaling, then device miniaturization is achieved, but current imbalance and BTI age effect worsen
Solution Approach 1:
The CFET structure implements local quality by providing spatially separated n-channel and p-channel regions with different structural characteristics. The nFET region has specific channel dimensions and doping profiles optimized for electron transport, while the pFET region has different dimensions optimized for hole transport, allowing each region to be locally optimized for its specific carrier type and reducing overall current imbalance and BTI susceptibility
Solution Approach 2:
The patent transitions from planar transistor architecture to three-dimensional vertically stacked CFET structure. The nFET and pFET are positioned in separate vertical stacks with controlled horizontal and vertical separations, allowing independent optimization of each transistor type's channel structure while maintaining compact footprint, thereby achieving both miniaturization and improved current stability
Data Source
AI summary
Disclosed are complementary field effect transistors (CFETs) with balanced n and p drive current, and methods for making the same. In an aspect, a CFET structure comprises an nFET with horizontal p-doped nanosheet channels arranged in a first vertical stack, each horizontal p-doped nanosheet channel having a width W1, and connecting a first source contact to a first drain contact through a first gate-all-around (GAA) region having a length L1. The CFET structure further comprises a pFET with horizontal n-doped nanosheet channels arranged in a second vertical stack disposed on the first vertical stack, each horizontal n-doped nanosheet channel having a width W2, and connecting a second source contact to a second drain contact through a second GAA region having a length L2, wherein W2/L2 is not equal to W1/L1.