CFET Nanosheet Gate Stack for Threshold Voltage Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving higher device density, performance, and lower costs through three-dimensional designs like nanosheet FETs, where further improvements are needed to enhance gate control and reduce short-channel effects.
Innovation Solution
A semiconductor device structure is developed with complementary field effect transistors (CFETs) that vertically stack n-channel and p-channel nanosheet FETs, utilizing interfacial layers and high-K dielectric layers doped or intermixed with p-dipole and n-dipole metals to achieve different threshold voltages, improving device reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then productivity and cost are improved, but gate control deteriorates and short-channel effects increase
Solution Approach 1:
The patent transitions from planar transistor design to three-dimensional nanosheet FET architecture, where the gate electrode completely surrounds the channel in multiple dimensions. This vertical stacking and wrap-around gate configuration provides enhanced gate control over the channel while maintaining reduced footprint, directly addressing the short-channel effects that arise from dimensional scaling.
Solution Approach 2:
The patent employs composite material structures including high-K dielectric layers combined with dipole metal layers (such as ScOx, YbOx, LuOx) to form the gate stack. This composite structure enables precise threshold voltage control and improved electrical characteristics, allowing the device to maintain reliability despite continued scaling to higher device densities.
2Ease of manufacture
If conventional planar FET design is used, then manufacturing is simpler, but gate control and performance are insufficient for advanced scaling
Solution Approach 1:
The patent segments the channel into multiple thin nanosheet layers stacked vertically, with gate electrodes wrapping around each channel segment. This segmentation approach maintains manufacturing feasibility through modular fabrication processes while achieving superior gate control compared to conventional planar designs, as each nanosheet can be independently controlled by the surrounding gate.
3Reliability
If nanosheet FET structure is implemented to improve gate control, then device density and performance are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions where sacrificial layers are first formed and precisely patterned before the actual nanosheet and gate structures are created. This preliminary structuring enables subsequent self-aligned fabrication steps, reducing the need for complex alignment procedures and minimizing manufacturing complexity despite the advanced three-dimensional architecture.
Data Source
AI summary
A semiconductor device structure is provided. The structure includes a first gate electrode layer having at least three surfaces surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material. The structure also includes a second gate electrode layer disposed below and in contact with the first gate electrode layer, the second gate electrode layer having at least three surfaces surrounded by a second intermixed layer, wherein the second intermixed layer comprises the first material and a fifth material, wherein the first gate electrode layer and the second gate electrode layer are disposed between two adjacent dielectric spacers.