CFET Nanosheet Fabrication with GeSn Mobility Enhancement
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Solution Overview
Problem
As semiconductor devices approach single-digit nanometer fabrication nodes, scaling challenges in 3D transistor fabrication hinder the achievement of high drive currents and efficient area scaling, necessitating innovative approaches to enhance transistor performance.
Innovation Solution
The use of complementary field-effect transistor (CFET) devices with nano-channels made of different materials, such as silicon, germanium, and germanium-tin, to provide strain and improve mobility, combined with a novel method of forming epitaxial layer stacks and gate structures that surround the nano-channels, allowing for efficient channel region formation without requiring new masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If 3D transistor fabrication is implemented to increase transistors per unit area, then area scaling is improved, but fabrication complexity and manufacturing challenges increase
Solution Approach 1:
The fabrication process is divided into separate epitaxial growth stages for forming different semiconductor material layers (e.g., GeSn, SiGe, Si). Each layer is deposited with specific thicknesses and compositions to create the 3D stacked transistor structure, breaking down the complex fabrication into manageable sequential steps
Solution Approach 2:
The patent transitions from traditional 2D planar transistors to 3D vertically-stacked transistors by growing semiconductor layers in the vertical dimension. Multiple transistor channels are stacked one above another, enabling higher density while using standard planar processing techniques adapted for vertical structures
2Area of moving object
If nanowire and nano sheet sizes are reduced to enable area scaling, then device area is reduced, but drive current decreases
Solution Approach 1:
Different semiconductor materials with distinct properties are used in different regions of the device. High-mobility materials like GeSn are placed in channel regions where high drive current is needed, while other materials are used in surrounding or adjacent regions, optimizing local electrical properties to maintain current despite reduced size
Solution Approach 2:
The device employs composite material structures including GeSn-SiGe-Si heterostructures. These composite materials combine the advantages of different semiconductors: GeSn provides high carrier mobility for high current, SiGe provides strain engineering capabilities, and Si provides lattice matching and stability, collectively maintaining drive current in scaled devices
3Reliability
If different materials are used in NMOS and PMOS channels to improve mobility, then carrier mobility is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The desired material composition and thickness profiles are established during the initial epitaxial growth process. By pre-defining the layer structure with appropriate materials (e.g., GeSn for NMOS, different composition for PMOS) before device fabrication begins, the need for complex post-growth material modification is eliminated
Solution Approach 2:
The patent controls material composition parameters during epitaxial growth, specifically varying Sn content in GeSn layers and Ge content in SiGe layers to achieve desired bandgap and mobility characteristics. By adjusting these compositional parameters during a single growth process, different material properties are achieved without adding process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility in n-type and p-type transistors, leading to improved saturation currents and optimized performance by adjusting bandgap values through varying Sn content in GeSn, enabling high-performance NMOS and PMOS transistors.
Implementation Method 1
an epitaxial layer stack over a substrate is formed. The epitaxial layer stack includes a plurality of intermediate layers, one or more first nano layers with a first bandgap value and one or more second nano layers
Implementation Method 2
A plurality of trenches are formed in the epitaxial layer stack. The plurality of intermediate layers are recessed so that the one or more first nano-channels and the one or more second nano-channels in each of the plurality of sub-stacks protrude from sidewalls of the plurality of intermediate layers
Data Source
AI summary
In a method for forming a semiconductor device, an epitaxial layer stack is formed over a substrate. The epitaxial layer stack includes intermediate layers, one or more first nano layers with a first bandgap value and one or more second nano layers with a second bandgap value. Trenches are formed in the epitaxial layer stack to separate the epitaxial layer stack into sub-stacks such that the one or more first nano layers are separated into first nano-channels, and the one or more second nano layers are separated into second nano-channels. The intermediate layers are recessed so that the first nano-channels and the second nano-channels in each of the sub-stacks protrude from sidewalls of the intermediate layers. Top source/drain (S/D) regions are formed in the trenches and in direct contact with the first nano-channels. Bottom source/drain (S/D) regions are formed in the trenches and in direct contact with the second nano-channels.