CFET Nanosheet Work Function Engineering for Threshold Voltage Control
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Solution Overview
Problem
Current technologies face challenges in providing multiple threshold voltages for n-type and p-type FETs in advanced semiconductor devices, particularly at nodes beyond 5 nm, which affects device performance and scaling.
Innovation Solution
The development of complementary field effect transistors (CFETs) with multiple voltage thresholds is achieved by using nanosheet structures with varying work function metals and gate contacts, including shared and independent configurations, to optimize switching delay and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple threshold voltage devices are implemented using conventional planar structures, then device performance can be optimized, but manufacturing complexity and cost escalate significantly at advanced nodes
Solution Approach 1:
The patent transitions from conventional planar FET structures to three-dimensional vertically stacked CFET architectures. By stacking nFET and pFET nanosheets vertically, the invention achieves multiple threshold voltage devices in a compact footprint while maintaining manufacturability at advanced nodes through standardized vertical fabrication processes
Solution Approach 2:
The invention divides the transistor channel into multiple discrete nanosheet segments stacked vertically. Each nanosheet can be independently controlled with separate gates, enabling multiple threshold voltage devices to be formed from a single stacked structure through selective gating, thereby reducing overall manufacturing complexity
2Quantity of substance
If chip scaling continues at current technology nodes, then device density increases, but process complexities and costs escalate
Solution Approach 1:
The patent employs vertical stacking of CFET devices to achieve high device density without proportionally increasing lateral footprint or process complexity. The vertical architecture allows multiple devices to be stacked along the z-axis, effectively utilizing three-dimensional space to pack more functionality into the same chip area while maintaining compatibility with existing fabrication processes
Solution Approach 2:
The vertically stacked CFET structure serves multiple functions simultaneously: it provides high device density, enables multiple threshold voltage devices, and maintains compatibility with standard semiconductor fabrication processes. The shared source/drain regions and common fabrication steps across stacked devices reduce overall process complexity despite increased device density
Data Source
AI summary
A CFET (complementary field effect transistor) structure including a substrate, a first CFET formed above the substrate, and a second CFET formed above the substrate. Each CFET includes a top FET and a bottom FET. Each of the top FET and bottom FET includes at least one nanosheet channel. The top FET of each CFET has a first polarity. The bottom FET of each a CFET comprises a second polarity. The top FET of the first CFET includes a first work function metal, and the top FET of the second CFET includes a second work function metal.