CFET NSFET Stacking with Dielectric Height Control
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving improved integration density and device performance in vertically stacked transistor devices, such as complementary field-effect transistor (CFET) devices, as existing architectures need further development to optimize nanostructure field-effect transistors (NSFETs).
Innovation Solution
A method involving the formation of NSFET devices with varying numbers of active nanostructures by controlling dielectric structure heights in source/drain openings, followed by bonding NSFET devices with interconnect structures to create a CFET device with vertically stacked NSFETs, utilizing epitaxial growth processes and advanced patterning techniques to form semiconductor fins and gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked transistor devices (CFETs) are formed to improve integration density, then integration density is improved, but device performance and nanostructure optimization need further development
Solution Approach 1:
The CFET device is segmented into multiple NSFETs stacked vertically, with each NSFET containing multiple nanostructures (nanosheets or nanowires) arranged in series. This segmentation allows independent optimization of each nanostructure layer while achieving high integration density through vertical stacking.
Solution Approach 2:
The patent transitions from planar transistor architecture to three-dimensional vertical stacking, utilizing the vertical dimension to increase device density. Multiple NSFETs are stacked along the vertical axis, with each NSFET containing multiple nanostructures stacked in series, effectively using spatial dimensionality to achieve higher integration density.
2Quantity of substance
If minimum feature sizes are reduced to increase integration density, then integration density is improved, but additional manufacturing and device performance problems arise
Solution Approach 1:
Multiple nanostructures are nested within each NSFET channel region, with nanosheets or nanowires stacked in series between source and drain regions. This nesting approach allows multiple functional elements to occupy a compact vertical space without requiring proportional increases in lateral feature sizes.
Solution Approach 2:
Semiconductor layers are formed with predetermined thicknesses and compositions through epitaxial growth before patterning. The alternating layers of first and second semiconductor materials are prepared in advance with controlled thicknesses, enabling subsequent self-aligned etching processes to form precise nanostructures without requiring extreme feature size control during final patterning.
3Quantity of substance
If more components are integrated into a given area, then integration density is improved, but device performance optimization becomes more challenging
Solution Approach 1:
Different regions of the CFET device can have different numbers of active nanostructures. The patent allows for selective formation of dielectric structures in different source/drain openings, enabling local optimization of device characteristics. Some regions may have more nanostructures for higher current capacity, while other regions have fewer nanostructures for lower power consumption.
Solution Approach 2:
The alternating layers of first and second semiconductor materials serve multiple functions: they form the channel regions for both N-type and P-type NSFETs, provide sacrificial material for self-aligned etching, and enable the formation of multiple nanostructures in series. This multi-functionality reduces the need for separate processing steps for different device components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances integration density and device performance by enabling efficient stacking and integration of NSFETs, improving current flow and reducing feature sizes, thereby advancing semiconductor device capabilities.
Implementation Method 1
a gate structure around the first nanostructures
Implementation Method 2
bonding the second interconnect structure to the first interconnect structure, wherein the bonding comprises performing a direct bonding between the second interconnect structure and the first interconnect structure without using a solder material
Data Source
AI summary
A semiconductor device includes: a first substrate; a first fin protruding above the first substrate; first nanostructures over the first fin; a first gate structure around the first nanostructures; a first source/drain region adjacent to the first gate structure and contacting a first subset of the first nanostructures; a first dielectric structure between the first source/drain region and the first fin, where the first dielectric structure contacts a second subset of the first nanostructures; second nanostructures over the first fin and laterally spaced apart from the first nanostructures; a second gate structure around the second nanostructures; and a second source/drain region adjacent to the second gate structure and contacting the second nanostructures.