CFET Layout With Opposite-Side Transistors to Prevent Thermal Damage
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, which can lead to deterioration in the quality of transistors when both p-type and n-type transistors are formed on the same side of a dielectric layer.
Innovation Solution
A method is developed to form complementary FETs (CFETs) where p-type and n-type transistors are formed on opposite sides of a dielectric layer, using high-mobility channel materials like Ge or Ge-rich SiGe for the p-type transistor and semiconductive oxide as a channel layer for the n-type transistor, allowing for lower processing temperatures and improved transistor quality by preventing thermal damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process difficulty increases and device reliability deteriorates
Solution Approach 1:
The patent divides the semiconductor device into two separate sides of a dielectric layer, with p-type transistors on one side and n-type transistors on the other side. This segmentation allows each transistor type to be optimized independently with appropriate thermal budgets, resolving the contradiction between maintaining device reliability and achieving high production efficiency at scaled dimensions.
Solution Approach 2:
The patent applies different thermal budgets to different regions of the device - p-type transistors receive one thermal budget while n-type transistors receive another. This local quality approach allows each region to be processed under optimal conditions for its specific requirements, maintaining reliability while enabling continued scaling for improved productivity.
2Device complexity
If p-type and n-type transistors are formed on the same side of a dielectric layer, then device complexity is reduced, but thermal damage occurs due to incompatible thermal budgets
Solution Approach 1:
Instead of placing p-type and n-type transistors on the same side (two-dimensional arrangement), the patent moves them to opposite sides of a dielectric layer (three-dimensional arrangement). This dimensional change allows both transistor types to coexist without thermal interference, eliminating thermal damage while maintaining reasonable device complexity.
3Ease of manufacture
If a single thermal budget is used for both p-type and n-type transistors, then manufacturing process is simplified, but thermal damage occurs to one or both transistor types
Solution Approach 1:
The manufacturing process is segmented into separate thermal processing steps for p-type and n-type transistors, with each side receiving its appropriate thermal budget. This segmentation maintains manufacturing simplicity by treating each transistor type independently while ensuring both achieve optimal quality without thermal damage.
Data Source
AI summary
A method includes forming a first dielectric layer over a substrate; forming a first transistor over a first side of the first dielectric layer; removing the substrate to expose a second side of the first dielectric layer opposite to the first side of the second dielectric layer; and forming a second transistor over the second side of the first dielectric layer. Forming the first transistor includes forming a semiconductor layer over the first side of the first dielectric layer; forming a first gate structure over the semiconductor layer; and forming source/drain epitaxy structures on opposite sides of the first gate structure. Forming the second transistor includes forming a semiconductive oxide layer over the second side of the first dielectric layer; forming a second gate structure over the semiconductive oxide layer; and forming source/drain contacts over the semiconductive oxide layer and on opposite sides of the second gate structure.