CFET Power Contact Structure Using Passing-Through Source/Drain Plugs
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced feature sizes, the formation of power contact plugs negatively affects chip area usage and channel widths, impacting transistor speed.
Innovation Solution
The formation of passing-through contact plugs that connect power from one side to the other side through source/drain regions without occupying additional chip area, allowing for different routing schemes and avoiding the need for deep power contact plugs that would otherwise extend beyond the source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep power contact plugs are formed to extend beyond source/drain regions, then power connection is achieved, but channel width and transistor speed are reduced
Solution Approach 1:
The patent transitions from vertical deep power contact plugs extending beyond source/drain regions to a dual-sided approach where power contacts are formed on both the front and back surfaces of the semiconductor device. This dimensional change allows power connection without compromising the channel width and transistor speed on the front surface.
Solution Approach 2:
The power connection function is segmented into two separate contact structures: front surface power contacts and back surface power contacts. This segmentation allows each contact to be optimized for its specific location, with back contacts providing power connection without interfering with the front surface channel region.
2Reliability
If deep power contact plugs are formed, then power connection is achieved, but additional chip area is occupied
Solution Approach 1:
By utilizing the back surface of the semiconductor device for power contacts, the patent effectively uses the third dimension (depth/thickness of the substrate) to resolve the area conflict. This allows power connection without occupying additional planar chip area.
3Reliability
If deep power contact plugs are formed, then power connection is achieved, but high aspect ratio issues arise
Solution Approach 1:
The power connection path is segmented into front surface contacts and back surface contacts, eliminating the need for single deep plugs with high aspect ratios. Each contact structure has a more manageable depth and aspect ratio suitable for standard fabrication processes.
Data Source
AI summary
A method includes forming a complementary field-effect transistor comprising forming a lower source/drain region, and forming an upper source/drain region over the lower source/drain region. An etching process is performed to etch-through the upper source/drain region and to form a contact opening. The etching process is stopped on a top surface of the lower source/drain region. The method further includes forming a dielectric contact spacer in the contact opening, forming a first silicide layer over the lower source/drain region, forming a contact plug over and contacting the first silicide layer, and forming a second silicide layer underlying and contacting a bottom surface of the lower source/drain region.