CFET Power Distribution via Parallel Metal Lines
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Solution Overview
Problem
Current integrated circuit (IC) power distribution designs face challenges in achieving improved routing flexibility and reduced parasitic capacitance without increasing area, particularly when power distribution metal lines are positioned perpendicular to gates of complementary field-effect transistors (CFETs).
Innovation Solution
The proposed solution involves positioning frontside and backside metal lines in the lowest metal layer, aligning them with the gates of CFETs, and configuring them to distribute power supply and reference voltages, which allows for improved routing flexibility and reduced parasitic capacitance without area penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If power distribution metal lines are positioned perpendicular to gates of CFETs, then routing flexibility is improved, but parasitic capacitance increases
Solution Approach 1:
The patent inverts the conventional power distribution approach by positioning metal lines parallel to CFET gates instead of perpendicular. This inversion resolves the contradiction by achieving both routing flexibility and reduced parasitic capacitance through the unconventional parallel alignment, which minimizes overlapping area between power lines and transistor gates.
Solution Approach 2:
The patent utilizes the third dimension (vertical stacking in 3D IC architecture) to resolve the routing contradiction. By distributing power lines across multiple metal layers in the vertical dimension and aligning them parallel to gates in the planar dimension, the design achieves routing flexibility without increasing parasitic capacitance in any single layer.
2Object-generated harmful factors
If power distribution metal lines are repositioned to align with CFET gates, then parasitic capacitance is reduced, but routing flexibility may be compromised
Solution Approach 1:
The patent makes the power distribution network multi-functional by implementing a unified parallel alignment rule for all metal lines relative to CFET gates. This universal approach simultaneously optimizes for both low parasitic capacitance and routing flexibility, allowing the same layout rule to serve multiple performance goals without compromise.
Solution Approach 2:
The patent introduces dynamic adaptability in routing by allowing metal lines to flexibly connect to CFET gates at optimal positions while maintaining parallel alignment. The routing paths can dynamically adjust within the parallel constraint framework, providing flexibility without violating the low-capacitance alignment rule.
3Power
If IC area is increased to improve power distribution, then power delivery capability is enhanced, but device miniaturization is compromised
Solution Approach 1:
The patent nests power distribution lines within the existing CFET gate alignment framework, utilizing the same spatial envelope. By nesting power lines parallel to and co-aligned with gate structures, the design achieves enhanced power delivery capability without requiring additional IC area, as the power distribution network is embedded within the transistor layout geometry.
Solution Approach 2:
The patent moves power distribution to the vertical dimension by utilizing multiple stacked metal layers. This 3D approach allows enhanced power delivery capability through increased vertical conductivity paths without expanding the planar IC area, thereby maintaining device miniaturization while improving power distribution performance.
Data Source
AI summary
An IC structure includes first and second complementary field-effect transistors (CFETs) positioned in a semiconductor wafer, each of the first and second CFETs including a gate structure extending in a first direction, an n-type channel extending through the gate structure in a second direction perpendicular to the first direction, and a p-type channel extending through the gate structure in the second direction and aligned with the n-type channel in a third direction perpendicular to each of the first and second directions. A metal line extends in the first direction, is aligned with each of the first and second CFETs in the third direction, and is configured to distribute a power supply or reference voltage to each of the first and second CFETs. The metal line is a metal line closest to each of the first and second CFETs along the third direction and extending in the first direction.