CFET Power Rail Layout for Low-Resistance Stacked Transistor Supply
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Solution Overview
Problem
Conventional CFET devices face challenges in efficiently routing power supply to stacked transistors due to limitations in the width and height of side rails, which restrict scalability and lead to high resistance and performance degradation.
Innovation Solution
The CFET structure incorporates a side power rail connected to a second power rail via contact structures, such as vias, allowing for a reduced height while maintaining electrical contact, thereby overcoming the limitations imposed by the tapered shape of the side rail.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the side rail width is increased to avoid high resistance, then the power delivery performance is improved, but the gate-cut restrictions and tapered shape limit the maximum height of the side rail
Solution Approach 1:
The power rail connection is segmented into two parts: a first power rail connected to the bottom transistor from below, and a second power rail connected to the top transistor via side rails. This segmentation allows each rail to be optimized independently, with side rails having reduced height requirements since they only need to connect to the second power rail level, not extend all the way to the bottom power rail level.
Solution Approach 2:
The second power rail acts as an intermediary element between the first power rail and the top transistor. By introducing this intermediate power distribution layer, the side rails no longer need to span the entire height from the bottom power rail to the top transistor, thereby reducing their height requirement and allowing wider widths for better power delivery performance.
2Reliability
If the side rail height is increased to reach the power rail, then the power supply connection is improved, but the tapered shape causes the bottom width to become too narrow
Solution Approach 1:
The vertical power distribution is segmented into multiple levels with the second power rail serving as an intermediate connection point. Side rails only need to extend from the transistor level down to the second power rail level, not all the way to the bottom of the device, thereby reducing the required height and allowing larger cross-sectional areas for better current carrying capacity.
3Ease of manufacture
If the side rail width is reduced to fit within gate-cut constraints, then the manufacturing feasibility is improved, but the resistance increases and power delivery degrades
Solution Approach 1:
The power distribution architecture transitions from a single vertical dimension to a multi-level hierarchical structure. By introducing the second power rail at an intermediate level, the side rails can have adequate width for low resistance while having reduced height, effectively using the vertical stacking dimension to resolve the width-height tradeoff.
Data Source
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AI summary
The disclosure relates to a complementary field effect transistor, CFET, structure (1) which comprises at least one CFET element (10) comprising a first transistor structure (21), and a second transistor structure (22) which is arranged above the first transistor structure (21). The CFET structure (1) further comprises: a first power rail (13) arranged below the CFET element (10), wherein the first power rail (13) is electrically connected to the first transistor structure (21) from below; a side power rail (17) arranged on one side of the CFET element (10), wherein the side power rail (17) is electrically connected to the second transistor structure (22) from the side; a second power rail (14) arranged below the CFET element (10); and at least one contact structure (18) which is arranged to electrically connect the second power rail (14) with the side power rail (17).