CFET Power Rail Layout for Top Transistor Supply Routing
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Solution Overview
Problem
Conventional CFET devices face challenges in routing power supply to top transistor structures due to the need for dedicated tap cells, which occupy a significant portion of the chip area and reduce the number of usable logic cells.
Innovation Solution
A CFET structure with a power rail below the first transistor structure and a power routing line above the second transistor structure, connected via a tap connection structure that bypasses the first transistor, allowing power supply from the backside to the frontside without requiring dedicated tap cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated tap cells are used to connect backside power supply to local power supply, then power supply to top transistor structures is achieved, but chip area is significantly reduced (4-5% area penalty)
Solution Approach 1:
The patent merges the power routing function directly into the CFET cell structure by integrating power routing lines with the transistor interconnect layers. Instead of using separate dedicated tap cells, the power routing is combined with the signal routing infrastructure already present in the CFET cell, eliminating the need for additional dedicated area for power connection.
Solution Approach 2:
The patent makes the CFET cell structure multi-functional by enabling the same interconnect layers and routing structures to serve both signal transmission and power distribution purposes. The power routing lines share the same physical infrastructure as the signal routing, allowing a single structure to perform multiple functions and eliminating redundant components.
2Productivity
If more CFET cells are packed to increase logic cell count, then device functionality is improved, but power routing complexity increases due to limited power supply access
Solution Approach 1:
The patent utilizes the vertical stacking dimension inherent in CFET structures to route power supplies. By arranging transistor structures in vertical stacks with multiple tiers, the power routing can proceed vertically through the stacked structure rather than requiring extensive lateral routing, thereby simplifying the power distribution network and enabling higher cell density.
Solution Approach 2:
The patent segments the power supply connection into hierarchical levels: backside power rails connect to intermediate power routing lines, which then connect to individual CFET cells. This segmented approach allows power to be distributed systematically across multiple cells without requiring complex direct connections to each cell, thereby reducing overall routing complexity.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
The disclosure relates to a CFET structure (10). The CFET structure (10) comprises at least one CFET element comprising a first transistor structure (21), and a second transistor structure (22) which is arranged above the first transistor structure (21) and which comprises a source and/or drain structure (12b). The CFET structure (10) further comprises a power rail (14) arranged below the first transistor structure (21) of the at least one CFET element; and a power routing line (16) arranged above the second transistor structure (22) of the at least one CFET element, wherein the power routing line (16) is electrically connected to the source and/or drain structure (12b) of the second transistor structure (22) from the top; wherein the at least one CFET element further comprises a tap connection structure (23) which is arranged to electrically connect the power rail (14) with the source and/or drain structure (12b) of the second transistor structure (22); wherein the tap connection structure (23) is arranged to bypass the first transistor structure (21) on one side.