CFET Power Rail and Signal Line Layout for Lower Resistance

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Solution Overview

Problem

Existing integrated circuits (ICs) with complementary field effect transistors (CFETs) face challenges in optimizing power connections and signal line configurations, leading to increased resistance and signal interference due to suboptimal positioning of power rails and signal lines.

Innovation Solution

The ICs employ a configuration where power rails and signal lines are positioned in both front-side and back-side conductive layers, with interlaced connections and shielding mechanisms to reduce resistance and improve signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power rails and signal lines are positioned in conventional single-layer configurations, then device complexity is reduced, but resistance increases and signal integrity deteriorates

Engineering Contradiction:

Improvesignal integrityVSAvoidconductive layer configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from conventional single-layer planar routing to multi-layer three-dimensional routing, placing power rails and signal lines in both front-side and back-side conductive layers. This vertical stacking approach reduces current path length and resistance while maintaining signal integrity through controlled impedance matching across layers.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The conductive system is segmented into multiple independent layers (front-side power rails, back-side power rails, front-side signal lines, back-side signal lines), allowing each layer to be optimized independently for its specific function while reducing interference between power and signal paths.

Inventive Principle:

Principle #1Segmentation

2Reliability

If power rails are positioned closer to CFET devices, then resistance is reduced, but signal interference increases

Engineering Contradiction:

Improvepower connection qualityVSAvoidsignal interference

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Power delivery and signal routing are segmented into separate conductive layers, with power rails in both front-side and back-side layers dedicated solely to power distribution, while signal lines occupy dedicated routing layers. This physical separation eliminates capacitive and inductive coupling between power and signal paths.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Insulating layers and via structures act as intermediaries between power rails and signal lines, providing electrical isolation while maintaining close physical proximity for efficient power delivery. The via structures serve as controlled impedance transitions that prevent signal reflection and interference.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If signal lines are routed through multiple layers, then signal integrity is improved, but manufacturing complexity increases

Engineering Contradiction:

Improvesignal shieldingVSAvoidconductive layer fabrication

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

Each conductive layer is designed to perform multiple functions: front-side power rails provide both power delivery and shielding for back-side signals, while back-side power rails similarly shield front-side signals. This multi-functionality reduces the total number of dedicated shielding structures needed.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The multi-layer conductive structure is nested within the CFET device stack, with conductive layers integrated between transistor layers rather than added as external components. This nesting approach allows simultaneous formation of multiple conductive layers during standard semiconductor fabrication processes.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS12588491B2Power rail and signal line arrangement in integrated circuits having stacked transistors

Publication Date: 2026.03.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An integrated circuit device includes a first-type transistor having a channel region in a first-type active-region semiconductor structure and a second-type transistor having a channel region in a second-type active-region semiconductor structure which is stacked with the first-type active-region semiconductor structure. In the integrated circuit, a front-side power rail and a front-side signal line in a front-side conductive layer extend in the first direction is, and a back-side power rail and a back-side signal line in a back-side conductive layer also extend in the first direction. The front-side conductive layer is above the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, while the back-side conductive layer is below the first-type active-region semiconductor structure and the second-type active-region semiconductor structure.