CFET Power Switch Layout for Strong Wake-Up in Compact ICs

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Solution Overview

Problem

Power switches with strong wake-up force occupy a large area in circuit systems, posing a challenge for reducing the footprint of advanced IC devices.

Innovation Solution

Implementing a power switch circuit using complementary field-effect transistors (CFETs) with stacked n-type and p-type devices, allowing for efficient power management without increasing the circuit's physical size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a power switch with strong wake-up force is implemented, then the operating speed is improved, but the area occupied in the circuit system increases

Engineering Contradiction:

Improveoperating speedVSAvoidcircuit area

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The patent implements CFET (Complementary Field-Effect Transistor) structures where nFET and pFET are stacked vertically in the same footprint area, transitioning from a planar two-dimensional layout to a three-dimensional vertical architecture. This allows the power switch to achieve strong wake-up force through enhanced current drive capability while maintaining a compact footprint by utilizing the vertical dimension for device stacking.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Power

If the power switch occupies a large area to provide strong wake-up force, then the power-up capability is improved, but the integration density of the IC device decreases

Engineering Contradiction:

Improvewake-up forceVSAvoidintegration density

Core Design Contradiction:

PowerVSProductivity

Solution Approach 1:

By stacking nFET and pFET devices vertically in CFET structures, the patent enables high power wake-up capability within a reduced planar footprint, thereby increasing integration density. The vertical stacking allows multiple transistor channels to be packed into the same area, improving both power performance and integration density simultaneously.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent combines nFET and pFET devices into integrated CFET structures where complementary transistors are stacked and share common regions such as source/drain areas and interconnect structures. This merging of complementary devices achieves strong wake-up force through enhanced current drive while reducing the total area required compared to separate discrete transistor implementations.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12562734B2Power switch circuit, IC structure of power switch circuit, and method of forming IC structure

Publication Date: 2026.02.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first control signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.