CFET Power Tap Layout Using Backside Power and Ground Grids
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Solution Overview
Problem
The challenges in semiconductor manufacturing include high process complexity and size reduction of features associated with gate electrodes and multilayer interconnect structures, which affect device area utilization, yield, and reliability, particularly in CFET devices.
Innovation Solution
The implementation of backside power and ground grids (BPG/BGG) for semiconductor devices, eliminating the need for vias and simplifying BEOL operations, thereby reducing patterning, etch, and deposition processes, and enhancing substrate area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional frontside power connections with vias are used, then power delivery is achieved, but device area utilization is reduced and manufacturing complexity increases
Solution Approach 1:
The patent inverts the conventional approach by moving power and ground connections from the frontside to the backside of the semiconductor device. The backside power grid (BPG) and backside ground grid (BGG) are formed on the backside surface, eliminating the need for complex via structures that would otherwise be required to establish power connections through the substrate. This inversion resolves the technical contradiction by simultaneously improving device area utilization and reducing manufacturing complexity.
Solution Approach 2:
The patent transitions power connection architecture from a two-dimensional frontside planar layout to a three-dimensional approach utilizing the backside surface. By forming power and ground grids on the backside of the substrate, the invention adds a spatial dimension to power delivery, allowing power connections to be established without occupying valuable frontside device area and without requiring complex via formation processes.
2Productivity
If backside power and ground grids are implemented, then device area utilization improves and manufacturing is simplified, but current/resistance losses must be managed
Solution Approach 1:
The patent merges the backside power grid (BPG) and backside ground grid (BGG) into an integrated backside interconnect architecture. By combining these two essential power delivery networks on the backside surface and connecting them to frontside power and ground lines through strategically positioned vias, the invention achieves simplified manufacturing while managing current and resistance losses through the unified grid structure.
Solution Approach 2:
The patent optimizes the electrical parameters of the backside power and ground grids by adjusting grid pattern geometry, conductor width, spacing, and material composition. These parameter changes are designed to minimize resistance and current losses while maintaining the manufacturing simplicity and area utilization benefits of the backside connection architecture.
Data Source
AI summary
A semiconductor device includes an intermediate layer including a plurality of conductive structures; and a plurality of isolation structures. The semiconductor device includes a first array of active regions on a first side of the intermediate layer. The semiconductor device includes a plurality of first gate structures, wherein corresponding first gate structures are between adjacent active regions of the first array of active regions. The semiconductor device includes a second array of active regions on a second side of the intermediate layer. The semiconductor device further includes a plurality of second gate structures, wherein corresponding second gate structures of the plurality of second gate structures are between adjacent active regions of the second array of active regions, each of the plurality of second gates is aligned with a corresponding first gate of the plurality of first gates, and a corresponding isolation structure is between aligned first and second gate structures.