CFET Local Interconnect Power Taps With Lower Parasitic Capacitance
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Solution Overview
Problem
Integrated circuit (IC) devices face challenges in reducing power tap area and optimizing power delivery structures, particularly in incorporating power tap cells within functional cells without disrupting gate connections between NMOS and PMOS transistors, and in managing parasitic capacitance associated with local interconnects.
Innovation Solution
The implementation of power tap structures embedded within functional circuits using local interconnects of complementary field-effect transistor (CFET) devices, with a dielectric material like low-k material around the interconnects to minimize parasitic capacitance, allowing for reduced power tap area and efficient power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If power tap structures are embedded within functional cells using local interconnects, then power tap area is reduced and routing resources are enhanced, but parasitic capacitance increases due to the presence of local interconnects
Solution Approach 1:
The patent embeds power tap structures within functional cells by nesting power tap cells inside functional cells. The power tap structure utilizes the local interconnects that already exist within the functional cell, effectively nesting one structure within another to reduce overall area without requiring additional external power tap structures.
Solution Approach 2:
The patent converts the harmful effect of local interconnects (which generate parasitic capacitance) into a beneficial feature by using these same interconnects to provide power tap functionality. The local interconnects that were previously only sources of parasitic capacitance are repurposed to carry power tap signals, thereby eliminating the need for separate power tap structures and reducing overall area.
2Device complexity
If power tap cells are integrated within functional cells, then device compactness is improved and routing resources are enhanced, but gate connections between NMOS and PMOS transistors may be disrupted
Solution Approach 1:
The patent applies local quality by selectively placing power tap structures at specific locations within functional cells where they can be integrated without disrupting critical gate connections. The power tap cells are positioned and configured to locally utilize available interconnect resources while preserving the integrity of NMOS and PMOS gate connections in other areas of the functional cell.
3Ease of manufacture
If local interconnects are used for power tap structures, then manufacturing process is simplified and area is reduced, but parasitic capacitance management becomes more challenging
Solution Approach 1:
The patent applies universality by designing local interconnects that serve multiple functions: they provide both signal routing within the functional cell and power tap functionality. This multi-functional approach simplifies the manufacturing process by eliminating the need for separate power tap interconnect structures, while the parasitic capacitance management is handled through careful design and placement of these universal interconnects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the power tap area and enhances routing resources within IC devices by integrating power tap cells within functional cells, while maintaining the integrity of gate connections and minimizing parasitic capacitance, thus improving the overall efficiency and design compactness of IC devices.
Implementation Method 1
minimize parasitic capacitance
Data Source
AI summary
An integrated circuit (IC) device includes a complementary field-effect transistor (CFET) device, a power rail at a first side of the CFET device, and a conductor at a second side of the CFET device. The CFET device includes a local interconnect. The first side is one of a front side and a back side of the CFET device. The second side is the other of the front side and the back side of the CFET device. The local interconnect of the CFET device electrically couples the power rail to the conductor.