CFET ROM Bit Cell Layout for Higher Density and Faster Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuit (IC) devices face challenges in reducing size and improving bit cell area and bit line delay in read-only memory (ROM) devices, particularly in complementary field effect transistor (CFET) configurations.
Innovation Solution
The implementation of a CFET device configuration where a top semiconductor device and a bottom semiconductor device store two bits of data independently, allowing for a high-density ROM device with improved bit cell area and a high-speed ROM device with reduced bit line delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single semiconductor device is used to store one bit of data, then the device structure is simple, but the bit cell area is large and density is low
Solution Approach 1:
The patent transitions from planar storage to three-dimensional stacked architecture by placing semiconductor devices in vertical stacks. Each stack contains multiple semiconductor devices (e.g., CFETs with top and bottom devices) that can store multiple bits independently, effectively utilizing the vertical dimension to increase storage density without increasing footprint area.
Solution Approach 2:
The patent implements nesting by placing semiconductor devices within stacked configurations where smaller functional units are contained within larger structural frameworks. Multiple semiconductor devices are nested within a single bit cell location, with each device contributing to the total storage capacity while sharing common interconnect structures.
2Speed
If single-ended sensing is used, then the sensing circuit is simple, but the bit line delay is large and read speed is slow
Solution Approach 1:
The patent divides the sensing function into separate top and bottom sensing circuits that operate independently on differential bit lines. This segmentation allows parallel sensing operations that reduce the effective sensing time and bit line delay, as both ends of the bit line can be sensed simultaneously rather than sequentially.
Solution Approach 2:
The patent inverts the conventional single-ended sensing approach by implementing differential sensing from both ends of the bit line. This inversion enables simultaneous sensing operations that reduce the time required to detect stored data, thereby increasing read speed despite the added circuit complexity.
3Quantity of substance
If CFET devices are stacked vertically, then the device density increases, but the manufacturing process becomes more complex
Solution Approach 1:
The patent addresses manufacturing complexity by transitioning to vertical stacking that leverages existing three-dimensional integration techniques. The CFET structure uses standard semiconductor fabrication processes extended to the vertical dimension, with gate electrodes and channels formed through established methods such as conformal deposition and etching that can be scaled to higher densities.
Data Source
AI summary
A read-only memory (ROM) device includes a complementary field effect transistor (CFET) device which has a first semiconductor device of a first type, and a second semiconductor device of a second type different from the first type. The second semiconductor device is under the first semiconductor device. A first word line is electrically coupled to a gate of the first semiconductor device. A second word line is electrically coupled to a gate of the second semiconductor device. The first semiconductor device is configured to store a first logic value. The second semiconductor device is configured to store a second logic value, independently of the first logic value stored in the first semiconductor device.