CFET Routing Layout With Topside-Backside Vertical Interconnects
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Solution Overview
Problem
Existing chip layouts face challenges in providing efficient power and signal routing for complementary field-effect transistors (CFETs), particularly in achieving maximum cell height reduction and effective P-N coupling.
Innovation Solution
The proposed solution involves a chip layout with stacked diffusion regions and rails, utilizing both topside and backside metal layers for signal routing and power distribution, which includes vertical connectors and vias to optimize routing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional planar routing is used for CFETs, then routing simplicity is maintained, but cell height cannot be minimized and routing congestion increases
Solution Approach 1:
The patent transitions from traditional planar (2D) routing to three-dimensional routing by utilizing both topside and backside metal layers. The diffusion regions are stacked vertically, and rails are positioned above and below the stacked regions, creating a 3D routing architecture that minimizes cell height while providing multiple routing paths through vertical connectors and vias.
Solution Approach 2:
The routing structure is segmented into multiple independent layers: topside metal layers for routing, backside metal layers for routing, and vertical connectors/vias for inter-layer connections. This segmentation allows each layer to be optimized independently for its specific routing function, reducing overall congestion and complexity.
2Length of moving object
If stacked diffusion regions are used, then cell height is reduced, but routing congestion increases due to limited access points
Solution Approach 1:
By utilizing both topside and backside metal layers, the patent creates additional routing dimensions. Vertical connectors and vias provide access points between the stacked diffusion regions and the rails, distributing routing traffic across multiple layers and reducing congestion in any single layer.
Solution Approach 2:
Vertical connectors and vias act as intermediaries between the stacked diffusion regions and the rails. These intermediary structures provide controlled access points that manage the connection between different routing layers, reducing direct congestion while maintaining electrical connectivity.
3Productivity
If multiple metal layers are used for routing, then routing efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming stacked diffusion regions, creating rails above and below, forming vertical connectors, and adding metal layers with vias. Each stage is independently optimized and can be performed using standard semiconductor fabrication techniques, managing manufacturing complexity while achieving high routing efficiency.
Data Source
AI summary
A chip includes a first diffusion region extending in a first direction, and a second diffusion region extending in the first direction, wherein the first diffusion region and the second diffusion region are stacked in a second direction perpendicular to the first direction. The chip also includes a first track extending in the first direction above the first diffusion region and a second track extending in the first direction below the second diffusion region. The chip also includes a first topside contact coupled between a first top surface of the first diffusion region and the first track, a first backside contact coupled between a first bottom surface of the second diffusion region and the second track, and a vertical connector coupled between the first track and the second track.