CFET Conductive Line Layout for Shared Power and Signal Shielding
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Solution Overview
Problem
Integrated circuits (ICs) face challenges in optimizing the performance of complementary field-effect transistors (CFETs) due to limitations in power and signal conductive line arrangements, which affect the pitch and flexibility of IC device design, leading to increased resistance and potential signal interference.
Innovation Solution
The implementation of asymmetric front-side and back-side arrangements of power, signal, and shielding conductive lines in CFETs, including shared power and shielding lines between neighboring transistors, and various connection methods such as source/drain connections, gate connections, and vias, to enhance routing resources and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If symmetric front-side and back-side arrangements of conductive lines are used, then manufacturing simplicity is maintained, but resistance increases and routing flexibility is limited
Solution Approach 1:
The patent applies asymmetry by configuring different arrangements of power and signal conductive lines on the front-side and back-side of the CFET. Specifically, the front-side has a first arrangement of conductive lines while the back-side has a second arrangement that is asymmetric relative to the front-side, optimizing electrical performance by reducing resistance and improving routing flexibility without requiring complex symmetric patterns
2Adaptability or versatility
If more conductive lines are added to improve routing resources, then signal interference increases and device complexity increases
Solution Approach 1:
The patent merges power and signal conductive lines into integrated conductive line structures that serve multiple functions. By combining these different types of conductive lines in specific asymmetric patterns on front and back sides, the design achieves improved routing resources while the integrated structure inherently reduces signal cross-talk through proper spacing and configuration
Solution Approach 2:
The patent utilizes the third dimension by implementing conductive line arrangements on both the front-side and back-side of the CFET. This vertical stacking approach allows routing resources to be expanded in the Z-dimension rather than only in the planar X-Y dimensions, reducing signal interference by separating conductive lines across different layers while maintaining compact device footprint
3Productivity
If pitch is reduced to increase device density, then manufacturing precision requirements increase and signal interference increases
Solution Approach 1:
The patent reduces pitch requirements by transitioning from planar routing to three-dimensional routing across front and back sides. This allows conductive lines to be spaced farther apart in the vertical dimension while maintaining high device density, thereby reducing signal interference and relaxing manufacturing precision requirements for pitch control
Data Source
AI summary
A method includes forming, over a substrate, adjacent first and second transistor stacks each including a first transistor, and a second transistor over the first transistor. A plurality of first conductive lines is formed in a first metal layer. The plurality of first conductive lines includes a power conductive line configured to route power to the first transistor stack, one or more signal conductive lines configured to route one or more signals to the first transistor stack, and a shielding conductive line configured to shield the routed one or more signals. The power conductive line or the shielding conductive line is shared with the second transistor stack.