CFET Shared Routing Layout for Compact Stacked Transistor Connectivity
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Solution Overview
Problem
Connecting stacked transistor structures in CFET devices to a backside power delivery network and facilitating signal exchange between them is challenging, leading to space inefficiencies and processing difficulties, especially in tight cell boundary scaling.
Innovation Solution
A CFET structure design where adjacent rows of transistor stacks share a single signal routing structure and power rails, with a symmetrical layout that includes a shared signal routing structure and power routing structures connected to each transistor, facilitated by spacer structures for alignment and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate signal routing structures are used for each CFET element, then electrical connection reliability is improved, but area consumption increases
Solution Approach 1:
The patent merges the signal routing structures of two adjacent CFET elements into a single shared routing structure. This shared structure is positioned between the two CFET elements and provides electrical connections to both elements simultaneously, thereby reducing the total area consumed while maintaining reliable electrical connections through the shared pathways.
2Reliability
If deep vias are used for signal routing, then connectivity between stacked transistors is improved, but processing difficulty increases
Solution Approach 1:
The patent transitions from vertical deep via routing to a lateral routing approach. The shared signal routing structure extends laterally between the two CFET elements rather than requiring deep vertical vias through the stacked transistor structures. This dimensional change from vertical to lateral routing simplifies the fabrication process while maintaining effective electrical connectivity between the stacked transistors and the BSPDN.
3Reliability
If more signal routing lines are provided for each CFET element, then electrical connectivity is improved, but space efficiency deteriorates
Solution Approach 1:
The shared signal routing structure serves multiple functions simultaneously: it provides electrical connections to both the first and second CFET elements, acts as a common pathway for signal and power distribution, and enables connectivity to the BSPDN for both elements. This multi-functional design ensures comprehensive electrical connectivity while maximizing space efficiency by eliminating redundant routing lines.
Data Source
AI summary
The disclosure relates to a complementary field effect transistor, CFET, structure. The CFET structure comprises: a first CFET element which is arranged in a first row of the CFET structure; and a second CFET element which is arranged in a second row of the CFET structure, wherein the second row is arranged laterally offset to the first row; wherein the first and the second CFET element each comprise: a first transistor structure, and a second transistor structure which is arranged above the first transistor structure. The CFET structure further comprises a shared signal routing structure which is arranged between the first and the second CFET element; wherein the shared signal routing structure is electrically connected to the first and/or the second transistor structure of the first and/or of the second CFET element, respectively.