CFET Side Rail Routing Layout for Low-Resistance Tier Connections
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Solution Overview
Problem
Conventional CFET designs face challenges in fabricating side routing connections between stacked transistor tiers without damaging other components, and in achieving low contact resistance for lateral contacts.
Innovation Solution
A method for processing a CFET device involves forming a fin structure with layer stacks, creating a trench in a buffer layer with shifted metal layers to form side rail structures, and establishing horizontal contact structures to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If side routing connections are fabricated between stacked transistor tiers, then electrical connectivity between top and bottom devices is achieved, but damage to other components (top epi, bottom MoA layer, isolation) occurs
Solution Approach 1:
The routing connection is segmented into two separate metal layers at different heights. The first metal layer connects to the bottom device while the second metal layer connects to the top device, with vertical vias providing the inter-layer connection. This segmentation allows each layer to be optimized for its specific connection requirements without compromising other components.
Solution Approach 2:
The routing solution transitions from a single-plane lateral connection to a multi-dimensional structure spanning two vertical tiers. By utilizing the vertical dimension with stacked metal layers and vias, the patent achieves three-dimensional routing that connects top and bottom devices without lateral interference with isolation structures.
2Reliability
If lateral contact is made with side routing line, then top and bottom transistor structures are connected, but contact resistance becomes large
Solution Approach 1:
The patent merges multiple contact functions into a unified vertical via structure that simultaneously connects the first metal layer to the second metal layer. This consolidated via structure, combined with optimized metal layer configurations, reduces overall contact resistance compared to separate lateral contact approaches.
Solution Approach 2:
The routing structure employs composite material stacks including multiple metal layers (first metal layer, second metal layer), dielectric materials (buffer layer, isolation layer), and via materials. This composite structure optimizes electrical conductivity while maintaining mechanical integrity and low contact resistance.
Data Source
Figure 1A~1F
Figure 2A~2B
Figure 3
AI summary
The disclosure relates to a method for processing a CFET device (10). The method comprises the steps of: forming a fin structure (23) comprising a first layer stack (23a) and a second layer stack (23b) above the first layer stack (23a); forming a trench (26) in a buffer layer (25) on one side of the fin structure (23), wherein the trench runs (26) in parallel to the fin structure (23); filling a first section of the trench (26) at least partially with a first metal layer (15), wherein the first metal layer (15) is arranged at a level of the first layer stack (23a); and filling a second section of the trench (26) at least partially with a second metal layer (16), wherein the second metal layer (16) is arranged at a level of the second layer stack (23b); wherein the first metal layer (15) and the second metal layer (16) are arranged shifted to each other in a direction along the length of the trench (26).