CFET Source/Drain Contact Structure With Selective Silicide Capping
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Solution Overview
Problem
In semiconductor manufacturing, particularly for sub-10 nanometer technology process nodes, existing complementary field effect transistors (C-FET) face challenges in forming metal silicide and source/drain contact materials due to small landing areas, leading to increased silicide-diffusion contact resistance and reduced performance.
Innovation Solution
A method is developed to selectively form metal silicide and a metal cap on the source/drain region of transistors using deposition processes like CVD or ALD, allowing these materials to be formed exclusively on the source/drain region rather than the surrounding dielectric, thereby reducing space occupation and improving contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal silicide and source/drain contact materials are formed using conventional methods, then the materials can be deposited on the source/drain region, but the small landing area leads to increased silicide-diffusion contact resistance
Solution Approach 1:
The patent segments the source/drain region into distinct zones: a first source/drain region with metal silicide for low resistance contact, and a second source/drain region without metal silicide for higher resistance contact. This segmentation allows different contact resistance characteristics in different areas, enabling the structure to achieve both low resistance where needed while maintaining manufacturability despite small overall landing area.
2Reliability
If deposition processes are used to form metal silicide and source/drain contact materials, then the materials can be formed on the source/drain region, but space occupation increases and contact resistance improves
Solution Approach 1:
The patent applies local quality by forming metal silicide selectively on specific portions of the source/drain region rather than uniformly across the entire region. The first source/drain region receives metal silicide deposition to achieve low contact resistance, while the second source/drain region remains without metal silicide. This localized application optimizes space utilization and reduces overall material occupation while maintaining excellent contact resistance where required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the silicide-diffusion contact resistance of integrated circuit structures by facilitating easier deposition and occupation of less space in the source/drain opening, leading to improved performance and reduced contact resistance.
Implementation Method 1
selectively forming a metal silicide and a metal cap on a source/drain region of a transistor other than a surrounding dielectric by a deposition process
Implementation Method 2
selectively forming a metal silicide and a metal cap on a source/drain region of a transistor other than a surrounding dielectric by a deposition process, such as a CVD or an ALD process
Data Source
AI summary
A method includes forming a bottom-tier transistor and a top-tier transistor over the bottom-tier transistor, the top-tier transistor comprising a first channel layer, a first gate structure around the first channel layer, and a plurality of first source/drain regions on opposite sides of the first channel layer; forming a first dielectric layer over the first source/drain regions of the top-tier transistor; etching the first dielectric layer to form a first opening exposing one of the first source/drain regions of the top-tier transistor; selectively forming a first metal silicide on the one of the first source/drain regions; selectively forming a first metal cap on the first metal silicide and not on the first dielectric layer; forming a front-side contact on the first metal cap.