CFET Source/Drain Silicide Layout for Low-Resistance Contacts
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, affecting production efficiency and cost.
Innovation Solution
The implementation of a complementary FET (CFET) structure with a 'silicide-first' process for forming metal silicide layers on source/drain epitaxy structures, which enhances contact area and reduces resistance, combined with a gate-all-around (GAA) transistor configuration using double-patterning or multi-patterning photolithography processes to create smaller pitches and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency improves and costs lower, but fabrication process difficulty increases and reliability decreases
Solution Approach 1:
The patent applies preliminary action by forming metal silicide layers on source/drain epitaxy structures before completing the transistor fabrication process. This 'silicide-first' approach pre-establishes low-resistance contact regions, making the subsequent fabrication process more manageable at smaller feature sizes and improving overall manufacturing ease
Solution Approach 2:
The patent segments the fabrication process into distinct stages: first forming metal silicide layers on source/drain structures, then proceeding with gate formation and other transistor fabrication steps. This segmentation allows each stage to be optimized independently, addressing the complexity of miniaturized fabrication
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency improves and costs lower, but device reliability worsens
Solution Approach 1:
By forming metal silicide layers preliminarily on source/drain epitaxy structures before final device completion, the patent ensures that critical contact regions have optimized electrical properties from the outset. This preliminary optimization of contact resistance and material properties enhances device reliability even as feature sizes shrink
Solution Approach 2:
The patent changes material parameters by using metal silicide layers with specific electrical properties on source/drain structures. This parameter optimization of contact resistance and material composition maintains device reliability during scaling to smaller feature sizes
3Reliability
If contact area between metal silicide layers and source/drain epitaxy structures is enlarged, then resistance decreases and device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of metal silicide layers with the source/drain epitaxy structure fabrication process. By combining these steps and forming silicide layers conformally on the epitaxy structures, the patent achieves enlarged contact area without proportionally increasing manufacturing complexity
Data Source
AI summary
A semiconductor device includes a first transistor, a second transistor, a first metal silicide layer, a second metal silicide layer, and an isolation structure. The first transistor includes a first channel layer, a first gate structure, and first source/drain epitaxy structures. The second transistor includes a second channel layer, a second gate structure, and second source/drain epitaxy structures. The first metal silicide layer is over one of the first source/drain epitaxy structures. The second metal silicide layer is over one of the second source/drain epitaxy structures. The isolation structure covers the one of the first source/drain epitaxy structures and the one of the second source/drain epitaxy structures, wherein in a cross-sectional view, the one of the first source/drain epitaxy structures is separated from the isolation structure through the first metal silicide layer, while the one of the second source/drain epitaxy structures is in contact with the isolation structure.