CFET Stacked Nanosheet Source/Drain Structure for Reliable Epitaxy
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Solution Overview
Problem
The challenge in vertically stacking gate-all-around transistors is the incomplete formation of upper source/drain regions through epitaxial growth, which can deteriorate the reliability of integrated circuit devices.
Innovation Solution
A semiconductor device design with vertically stacked channel layers, featuring a lower and upper source/drain region with specific impurity layers, including a side impurity layer extending vertically and a center impurity layer with a curved shape, to ensure complete formation and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If upper source/drain is formed only by epitaxial growth, then manufacturing process is simplified, but source/drain region formation is incomplete and reliability deteriorates
Solution Approach 1:
The upper source/drain region formation process is segmented into multiple steps: first forming a sacrificial layer, then performing selective epitaxial growth to form the source/drain region, and finally removing the sacrificial layer. This segmentation allows complete and controlled formation of the source/drain region while maintaining manufacturing feasibility.
Solution Approach 2:
A sacrificial layer is formed in advance before the source/drain region formation. This preliminary action creates a defined space and template for the subsequent epitaxial growth, ensuring that the source/drain region forms completely and correctly in the intended location.
2Productivity
If transistors are vertically stacked to increase integration density, then cell interference is minimized and more transistors are integrated in narrow space, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar transistor arrangement to vertical stacking, utilizing the third dimension (height) to increase integration density. Multiple transistor layers are stacked vertically with gate lines extending in horizontal directions, allowing more transistors to be integrated in a narrow footprint while maintaining manufacturability through systematic process design.
Data Source
AI summary
A semiconductor device includes: a lower stack including a plurality of lower gate lines and a plurality of lower nanosheets that are alternately stacked on a substrate; an upper stack including a plurality of upper gate lines and a plurality of upper nanosheets that are alternately stacked on the lower stack; a lower source/drain region disposed on a side surface of the lower stack; and an upper source/drain region disposed on the lower source/drain region and adjacent to a side surface of the upper stack, wherein the upper source/drain region includes a side impurity layer and an upper center impurity layer, wherein the side impurity layer extends in a vertical direction along the side surface of the upper stack, and the upper center impurity layer is disposed on an inner side of the side impurity layer, and a first surface of the upper center impurity layer has a curved shape.