Work Function Metal Patterning in Nanosheet CFETs With Spacer Masking
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Solution Overview
Problem
The fabrication of stacked nanosheet complementary field effect transistors (CFETs) is challenging due to difficulties in selectively masking devices, leading to poor power efficiency, structural stability, and complex fabrication processes, especially because the close proximity of upper and lower devices causes masking material to pinch off and incompletely fill the space between them.
Innovation Solution
A sacrificial layer is used to create a greater distance between the upper and lower device regions, allowing for complete masking of the lower device during processing of the upper device, including the deposition of different work function metals, thereby improving the fabrication process and device stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked CFETs are formed with close proximity between upper and lower devices, then device density is increased, but masking material pinches off and cannot completely fill the space between devices
Solution Approach 1:
The patent introduces a dielectric spacer layer that segments the space between upper and lower device regions, creating physical separation that prevents masking material pinch-off while maintaining high device density. The spacer acts as an intermediary structure that divides the continuous space into separated zones.
Solution Approach 2:
The dielectric spacer layer serves as an intermediary element between the upper and lower devices, providing the necessary separation distance for complete masking material deposition. This mediator structure enables the masking process to proceed without the pinch-off effect that occurs in direct close-proximity configurations.
2Quantity of substance
If different FET structures are stacked to improve device density, then space utilization is increased, but structural stability deteriorates
Solution Approach 1:
The dielectric spacer layer provides beforehand cushioning between the upper and lower FET structures, preventing structural interference and damage. This pre-positioned protective layer ensures that subsequent processing steps do not compromise the structural integrity of either device region.
Solution Approach 2:
The patent uses different dielectric materials with distinct properties (analogous to color changes) to differentiate and protect various structural regions. The spacer layer's specific dielectric properties provide both electrical isolation and mechanical support for structural stability.
3Device complexity
If masking is performed without sufficient separation distance, then fabrication process complexity is reduced, but device damage occurs during processing
Solution Approach 1:
The dielectric spacer layer is formed in advance before the masking and work function metal deposition steps. This preliminary action establishes the necessary separation geometry upfront, enabling subsequent processing to proceed without complexity while protecting against device damage.
4Loss of time
If work function metals are deposited without complete masking, then processing time is reduced, but power efficiency deteriorates
Solution Approach 1:
The dielectric spacer segments the device structure into clearly separated upper and lower regions, enabling complete and clean masking of one region during work function metal deposition. This segmentation ensures that the correct metal is deposited on the correct device region, guaranteeing proper electrical characteristics and power efficiency.
Data Source
AI summary
Semiconductor devices, and methods of forming the same, include forming a stack of channel layers, including an upper device region and a lower device region. The upper device region is separated from the lower device region by a dielectric spacer layer. A first work function metal layer is formed on the channel layers in the lower device region. A height of the first work function metal layer does not rise above the dielectric spacer layer. A second work function metal layer is formed on the channel layers in the upper device region.