CFET Inner Spacer Width Tuning for Capacitance and On-Current
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Solution Overview
Problem
The integration of complementary FET (CFET) devices in semiconductor manufacturing is challenging due to the complexity introduced by miniaturization, requiring improved fabrication methods to enhance device performance and efficiency.
Innovation Solution
The implementation of CFET structures with inner spacers of varying widths for p-type and n-type transistors, where thicker spacers reduce capacitance and thinner spacers enhance on-current, is employed to improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner spacers with uniform width are used for both p-type and n-type transistors, then manufacturing process is simpler, but device performance is suboptimal due to inability to independently optimize capacitance and on-current
Solution Approach 1:
The patent applies local quality by forming first inner spacers with a first width for the n-type transistor and second inner spacers with a second width for the p-type transistor. This allows each transistor type to have optimally sized spacers tailored to its specific electrical characteristics, enabling independent optimization of capacitance and on-current for each device type while maintaining a relatively simple fabrication process through selective etching.
2Productivity
If miniaturization is pursued to improve production efficiency and lower costs, then scaling down dimensions is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the spacer structure into distinct first inner spacers and second inner spacers with different widths for n-type and p-type transistors respectively. This segmentation allows independent optimization of each transistor type's electrical characteristics while maintaining scalability for mass production, thereby improving production efficiency without excessively increasing manufacturing process complexity.
3Loss of energy
If thicker inner spacers are used, then capacitance is reduced, but on-current decreases
Solution Approach 1:
The patent resolves this contradiction by applying local quality through differentiated spacer widths: first inner spacers with a first width are formed for the n-type transistor to optimize its on-current, while second inner spacers with a second width are formed for the p-type transistor to optimize its capacitance. This localized optimization allows each transistor type to achieve its optimal balance between capacitance and on-current without compromising the other.
Data Source
AI summary
A semiconductor device structure includes first nanostructures formed over a substrate. The structure also includes a first gate structure wrapped around the first nanostructures. The structure also includes first source/drain epitaxial structures formed over opposite sides of the first nanostructures. The structure also includes first inner spacers formed between the first gate structure and the first source/drain epitaxial structures. The structure also includes second nanostructures formed over the first nanostructures. The structure also includes a second gate structure wrapped around the second nanostructures. The structure also includes second source/drain epitaxial structures formed over opposite sides of the second nanostructures. The structure also includes second inner spacers formed between the second gate structure and the second source/drain epitaxial structures. The first inner spacers and the second inner spacers have different widths.