CFET SRAM Cell Layout for Balanced Bit Line Capacitance
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Solution Overview
Problem
The scaling down of transistors in semiconductor storage devices has led to increased off-current and power consumption, which is not effectively addressed by existing technologies.
Innovation Solution
A layout structure for an SRAM cell using complementary FET (CFET) devices, where transistors are arranged such that bit line contacts are aligned in the same direction, maintaining balanced load capacitance between complementary bit line pairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistors are scaled down to improve integration degree and operating speed, then device density and speed increase, but off current increases and power consumption increases significantly
Solution Approach 1:
The patent transitions from conventional planar transistors to three-dimensional stacked CFET structures, where n-type and p-type FETs are vertically stacked. This dimensional change enables better control of off-current through improved gate control in the vertical configuration, while maintaining high integration density, thus reducing power consumption without sacrificing operating speed.
2Productivity
If transistors are scaled down to increase integration degree, then device density improves, but off current increases leading to higher power consumption
Solution Approach 1:
By stacking n-type and p-type FETs vertically in a CFET configuration, the patent achieves high integration density in the vertical dimension while maintaining effective gate control. This three-dimensional structure reduces off-current leakage compared to planar scaling, thereby lowering power consumption while preserving integration degree.
3Adaptability or versatility
If bit line contacts are not aligned in the same direction, then layout flexibility increases, but load capacitance balance between complementary bit lines deteriorates
Solution Approach 1:
The patent employs asymmetric layout design where bit line contacts are deliberately aligned in the same direction to achieve capacitance balance between complementary bit lines. This asymmetric arrangement optimizes the electrical characteristics by ensuring equal load capacitance, which is critical for reliable differential signal operation in SRAM cells.
4Ease of manufacture
If conventional planar transistor structures are used, then manufacturing process is simpler, but off current control is insufficient leading to high power consumption
Solution Approach 1:
The patent implements three-dimensional stacked CFET structures that provide superior off-current control through enhanced gate control in the vertical configuration. While the manufacturing process becomes more complex compared to planar structures, the significant reduction in power consumption justifies the increased manufacturing sophistication.
Data Source
AI summary
Static Random Access Memory (SRAM) cell using Complementary FET (CFET) includes the first to sixth transistors each of which is a three-dimensional transistor. The first to fourth transistors are formed at the same position as each other in the first direction in which channel portions of the first to sixth transistors extend. The fifth transistor having a node connected to the first bit line and the sixth transistor having a node connected to the second bit line are formed at the same position in the first direction as each other.