3D CFET SRAM Cell Layout for Lower Power and Smaller Area
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Solution Overview
Problem
The scaling down of transistors in semiconductor storage devices has led to increased off-current and power consumption, necessitating the development of three-dimensional transistors to improve integration, reduce voltage, and enhance speed, but no effective layout structure for two-port SRAM cells using complementary FETs (CFETs) has been established.
Innovation Solution
A layout structure for a two-port SRAM cell is implemented using CFETs, where transistors are stacked in multiple layers with specific connectivity and conductivity types, allowing for efficient data read/write operations and reduced area utilization through the use of three-dimensional transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor gate length is scaled down to improve integration degree and operating speed, then integration degree and operating speed are improved, but off current increases and power consumption increases significantly
Solution Approach 1:
The patent transitions from planar two-dimensional transistor structures to three-dimensional vertically stacked CFET structures. By stacking n-type and p-type FETs vertically, the invention achieves higher integration density in the vertical dimension while maintaining controlled off-current characteristics through the three-dimensional device structure, thereby resolving the contradiction between integration improvement and power consumption increase.
2Ease of manufacture
If conventional planar transistor structures are used, then manufacturing is simpler, but integration degree is limited and area utilization is poor
Solution Approach 1:
The patent employs vertically stacked CFET structures that utilize the third dimension (vertical stacking) to achieve high integration density. Multiple n-type and p-type FETs are stacked along the vertical axis, enabling compact cell layouts and improved area utilization while maintaining compatibility with existing semiconductor manufacturing processes.
3Productivity
If three-dimensional CFET structures are implemented, then integration degree improves and area is reduced, but device complexity increases
Solution Approach 1:
The patent divides the SRAM cell into distinct functional blocks including stacked CFET structures for memory cells, separate bit line pairs for dual-port access, and dedicated word line structures. This segmentation allows each component to be optimized independently while maintaining overall system functionality, managing device complexity through modular design.
Solution Approach 2:
The vertically stacked CFET structures serve multiple functions: they provide both n-type and p-type transistor functionality in a compact footprint, enable dual-port SRAM operation through shared structures, and maintain scalability for further integration. This multi-functionality reduces overall device complexity by consolidating multiple functions into unified structures.
Data Source
AI summary
Transistors N1, N5 corresponding to a drive transistor PD1 are formed in a cell lower part and a cell upper part, respectively, and transistors N2, N6 corresponding to a drive transistor PD2 are formed in the cell lower part and the cell upper part, respectively. A transistor P1 corresponding to a load transistor PU2 is formed in the cell lower part, and a transistor P2 corresponding to a load transistor PU1 is formed in the cell upper part.