CFET SRAM Cell Structure for Higher Density and Lower Resistance
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Solution Overview
Problem
Static Random-Access Memory (SRAM) faces scalability issues due to lithography challenges and interconnect limitations, leading to reduced density and degraded read/write performance in on-chip memory designs.
Innovation Solution
Implementing complementary field-effect transistor (CFET) technology with vertically stacked nMOS and pMOS transistors and incorporating intermediate metal (IM) layers between these transistors to enhance routing and interconnect efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional SRAM cell structure is used, then manufacturing process is simple, but cell density is reduced and read/write performance is degraded
Solution Approach 1:
The patent transitions from planar transistor arrangement to vertical stacking of nMOS and pMOS transistors in alternating layers. This three-dimensional configuration increases cell density by utilizing the vertical dimension, allowing more transistors per unit area while maintaining simplified routing through intermediate metal layers.
Solution Approach 2:
The SRAM cell is divided into separate nMOS and pMOS transistor layers with intermediate metal routing layers positioned between them. This segmentation allows independent optimization of transistor placement and routing, reducing interconnect complexity while increasing density.
2Reliability
If conventional planar routing is used, then routing is simple, but interconnect resistance increases and performance degrades
Solution Approach 1:
The patent introduces intermediate metal routing layers positioned between the nMOS and pMOS transistor layers. This vertical routing dimension reduces interconnect resistance by providing shorter, more direct pathways for signal transmission, thereby improving read/write performance without significantly increasing overall device complexity.
3Area of moving object
If lithography process is scaled down, then device size decreases, but manufacturing precision deteriorates due to lithography challenges
Solution Approach 1:
By stacking transistors vertically and routing signals through intermediate metal layers, the patent reduces the lateral footprint of SRAM cells. This dimensional transition allows smaller cell area that can be manufactured with conventional lithography processes, avoiding the precision challenges of extreme scaling while maintaining high density.
Data Source
AI summary
Embodiments herein relate to a memory cell having n-type metal-oxide-semiconductor field-effect transistor (nMOSFETs) in one layer in the cell and pMOSFET transistors in another, lower layer of the cell, and one or more intermediate metal (IM) layers between the nMOS and pMOS transistors. The IM layers can provide routing between the nMOS and pMOS transistors, to one or more top metal layers, above the nMOS transistors, and to one or more bottom metal layers, below the pMOS transistors. An example six-transistor cell can include four nMOS transistors and two pMOS transistors, and an example eight-transistor cell can include four nMOS transistors and four pMOS transistors.