3P3N CFET SRAM Cell Layout for Stable Single-Bitline Writes
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Solution Overview
Problem
Conventional SRAM cells face challenges in reducing size and improving integration due to their complex structure and difficulty in performing write operations, particularly when using CFET technology with 3 P-channel and 3 N-channel transistors.
Innovation Solution
The SRAM cell structure is redesigned with 3 P-channel and 3 N-channel transistors, utilizing vertically stacked CFET technology, with specific driving capability conditions for each transistor to ensure stable read and write operations, and operates using only the BL signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM cell structure with 6 transistors (4 N-channel and 2 P-channel) is used, then the SRAM can operate faster and more stably than DRAM, but the cell size is larger and integration density is lower
Solution Approach 1:
The patent applies CFET (Complementary Field-Effect Transistor) technology to stack N-channel and P-channel transistors vertically in three dimensions. This vertical stacking approach transitions from a planar 2D layout to a 3D structure, allowing two transistors to occupy the area of one transistor, thereby reducing cell area by ideally 50% while maintaining operational stability through proper transistor configuration and sizing ratios
2Productivity
If CFET technology is applied to conventional 6T SRAM cell, then transistor density increases, but the structure becomes more complex and write operations become difficult
Solution Approach 1:
The patent segments the SRAM cell into distinct functional blocks: two cross-coupled inverters (each with one N-channel and one P-channel transistor in vertical stack) and two access transistors (one N-channel and one P-channel). This segmentation allows independent optimization of each transistor's driving capability, simplifying the design of write operations while maintaining high transistor density through vertical stacking
Solution Approach 2:
The patent assigns different driving capability ratios to different transistor pairs within the cell. Specifically, the N-channel access transistor has a driving capability ratio of 0.5-0.7 relative to its P-channel counterpart, while the N-channel inverter transistor has a ratio of 0.3-0.5 relative to its P-channel counterpart. This local differentiation of transistor characteristics enables stable write operations in the vertically stacked CFET structure
3Area of stationary object
If access transistors are composed of both NMOSFET and PMOSFET in 3P3N structure, then cell area is minimized, but gate overdrive voltage is lowered and write operations become difficult
Solution Approach 1:
The patent changes the critical parameter of transistor driving capability ratio to enable write operations in the minimized 3P3N structure. By setting the N-channel access transistor driving capability to 0.5-0.7 times that of the P-channel access transistor, and the N-channel inverter transistor to 0.3-0.5 times that of the P-channel inverter transistor, the patent compensates for the lowered gate overdrive voltage in the vertically stacked CFET configuration, enabling stable write operations while maintaining minimal cell area
Data Source
AI summary
Provided is an SRAM cell structure having 3 P-channel transistors and 3 N-channel transistors. The SRAM cell device includes a first inverter composed of a CMOS; a second inverter composed of a CMOS, the input terminal of which is connected to the output terminal of the first inverter, and the output terminal of which is connected to the input terminal of the first inverter; a first access transistor connected between the bit line (BL) and the input terminal of the first inverter; and a second access transistor connected in parallel with the first access transistor. The first access transistor is composed of an N-channel transistor and is switched by the WL signal. The second access transistor is composed of a P-channel transistor and is switched by the inverse signal (WWL) of the WRITE signal.