CFET SRAM Cell Layout Using Vertical Transistor Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing CFET structures for multi-port SRAM cells inefficiently use area, leading to challenges in integrating them into advanced integrated circuits due to the disproportionate number of transistors at different levels, particularly affecting 8T SRAM cells.
Innovation Solution
A semiconductor device with a CFET structure is designed to have first and second frontside levels for forming different conductive type transistors, allowing for a 7T SRAM cell configuration with transistors vertically stacked, eliminating the need for additional active area and enabling seamless integration into advanced integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If CFET structures are used for multi-port SRAM cells, then transistor density increases, but area utilization becomes inefficient due to disproportionate transistor distribution at different levels
Solution Approach 1:
The patent transitions from planar transistor arrangement to vertical stacking configuration, utilizing the third dimension (height) to increase transistor density. Multiple transistors are stacked vertically to form columns, allowing more transistors to be packed into the same footprint area without compromising area utilization efficiency.
Solution Approach 2:
The CFET structure is segmented into distinct levels (first level with first transistors, second level with second transistors) with selective electrical connections. This segmentation allows independent optimization of each level's transistor configuration, enabling efficient area utilization while maintaining high overall density through selective inter-level connectivity.
2Adaptability or versatility
If additional active area is allocated for 8T SRAM cells, then transistor configuration flexibility improves, but integration density decreases
Solution Approach 1:
The CFET structure provides universal functionality by enabling multiple transistor configurations (6T, 7T, 8T SRAM cells) within the same vertical stacking framework. The selective electrical connection mechanism allows the same physical structure to serve different circuit functions, achieving configuration flexibility without requiring additional active area for each cell type.
Solution Approach 2:
Multiple transistor functions are merged into a single vertical stack, where first and second transistors at different levels work together to form complete circuit elements. This merging consolidates what would traditionally require separate planar areas into a compact vertical unit, maintaining integration density while providing the flexibility of various SRAM cell configurations.
Data Source
AI summary
A memory device includes a substrate having a first side and a second side opposite to each other; a first transistor, a second transistor, and a third transistor formed at a first level on the first side of the substrate, the first to third transistors each formed with a first conductivity; and a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor formed at a second level on the first side of the substrate, the fourth to seventh transistors each formed with a second conductivity, wherein the first level is vertically disposed with respect to the second level. The first to seventh transistors operatively form a Static Random Access Memory (SRAM) cell.