CFET SRAM Layout With Work-Function Tuning for Faster Low-Voltage Reads
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Solution Overview
Problem
Existing integrated circuits (ICs) face challenges in achieving high-speed operation at reduced power supply levels due to limitations in the design and manufacturing of pass-gate and pull-down transistors, which affect read current properties and power consumption.
Innovation Solution
Incorporating complementary field-effect transistors (CFETs) with pass-gate and pull-down transistors having different work function configurations, allowing for tunable threshold voltage levels, thereby improving read current properties and enabling operation at reduced power supply levels with higher operating speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional transistor design is used, then device structure is simple, but read current properties are insufficient and operating speed is limited
Solution Approach 1:
The transistor gate is segmented into two independent gates (first gate and second gate) with different work function configurations. This segmentation allows independent control of threshold voltages to optimize read current properties and operating speed without compromising structural simplicity
Solution Approach 2:
Different regions of the transistor gate are assigned different work function configurations - the first gate has a first work function configuration while the second gate has a second work function configuration. This local quality differentiation enables tailored threshold voltage control for specific circuit performance requirements
2Speed
If higher power supply levels are used, then operating speed increases, but power consumption increases
Solution Approach 1:
The invention changes the parameter of work function configuration by providing two distinct gates with different work functions. This enables independent adjustment of threshold voltages to maximize read current at lower supply voltages, achieving high-speed operation without proportionally increasing power consumption
3Reliability
If transistor threshold voltage is increased, then read current improves, but power supply level must be increased
Solution Approach 1:
By segmenting the gate into two independently controllable gates with different work functions, the invention enables optimization of threshold voltage for read current performance without requiring a proportional increase in power supply level, as each gate can be tuned to its optimal voltage
Solution Approach 2:
The invention introduces work function configuration as a controllable parameter through different gate materials or structures. This allows direct adjustment of threshold voltage to improve read current properties while maintaining the same power supply level
Data Source
AI summary
An IC device includes a static random-access memory (SRAM) device positioned in a substrate, the SRAM device including a first complementary field-effect transistor (CFET) including a first pass-gate transistor positioned at a first elevation, a second CFET including a first pull-down transistor positioned at the first elevation and a first pull-up transistor positioned at a second elevation, a third CFET including a second pull-down transistor positioned at the first elevation and a second pull-up transistor positioned at the second elevation, and a fourth CFET including a second pass-gate transistor positioned at the first elevation. Each of the first and second pull-down transistors includes a gate extending in a gate direction and including a first work function configuration, and each of the first and second pass-gate transistors includes a gate extending in the gate direction and including a second work function configuration different from the first work function configuration.