CFET Vertical Stack Layout for Simpler Source-Drain Routing
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Solution Overview
Problem
The increasing density of integrated circuits (ICs) leads to design and fabrication challenges due to the complexity of routing conductive traces and the need for precise alignment of source and drain contacts, which can result in manufacturing errors and reduced packing efficiency.
Innovation Solution
A vertical stack of field-effect transistors (FETs) with fully independent source and drain contacts and a common gate, where the source and drain contacts of upper FETs are offset along the gate direction, allowing for increased routing flexibility and improved packing density by routing all metal lines in one direction on each metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC density is increased, then functionality and speed are improved, but design and fabrication complexity increases
Solution Approach 1:
The patent transitions from planar 2D routing to 3D vertical stacking, where multiple FET layers are stacked vertically with source/drain contacts extending through intermediate layers. This dimensional change allows routing to occur in the vertical dimension rather than only horizontally, significantly reducing lateral routing complexity while increasing IC density.
Solution Approach 2:
The patent divides the IC structure into multiple discrete FET layers stacked vertically, with each layer containing FETs that can be independently configured. This segmentation allows complex circuits to be built by stacking simpler FET units, reducing overall routing complexity while maintaining high functionality.
2Productivity
If IC density is increased, then functionality and speed are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements a nested structure where source/drain contacts of upper FET layers are positioned within or adjacent to the source/drain contacts of lower layers, creating a vertically integrated contact structure. This nesting allows shared fabrication processes for contacts across multiple layers, reducing alignment precision requirements while enabling high IC density.
Solution Approach 2:
The patent merges source/drain contacts from multiple FET layers into a single vertically integrated contact structure that serves multiple FETs across different layers. This merging reduces the number of separate alignment operations required, as one contact structure fulfills multiple functions, thereby reducing manufacturing precision requirements.
3Device complexity
If conventional routing is used, then design simplicity is maintained, but packing efficiency decreases
Solution Approach 1:
The patent utilizes vertical stacking to achieve three-dimensional packing of FETs, where multiple layers are stacked above a common substrate. This allows much higher packing efficiency by utilizing the vertical dimension, while routing is simplified by having source/drain contacts that extend vertically to provide direct access to all FET layers.
Data Source
AI summary
A complementary field effect transistor (CFET) structure includes a vertical stack of first and second transistors, wherein the first transistor includes a first channel extending in a first direction from a first source/drain (S/D) region to a second S/D region through a gate extending in a second direction perpendicular to the first direction and the second transistor includes a second channel extending in the first direction from a third S/D region to a fourth S/D region through the gate. A first conductive trace extends in the first direction over the gate, a first via extends from the first S/D region to the first conductive trace and is aligned with the third S/D region along the second direction, a second via extends from the fourth S/D region to the first conductive trace, and the first via has a first height greater than a second height of the second via.