CFET Sub-Stack Etching for Pass Gate Formation
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Solution Overview
Problem
Existing semiconductor technologies face challenges in efficiently forming non-stacked transistor devices from stacked CMOS devices, such as CFETs, which lack a pass gate function due to shared gate electrodes, limiting their functionality in integrated circuits requiring both CMOS and non-CMOS devices.
Innovation Solution
A method is developed to form non-stacked transistor devices by etching a cut through the top device sub-stack of a stacked CMOS device structure, preserving the bottom channel layers and forming a functional gate stack on the bottom device sub-stack, allowing for the creation of non-stacked devices alongside stacked ones on the same substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a common gate electrode is used in CFET devices to reduce footprint, then area efficiency is improved, but pass gate function is lost
Solution Approach 1:
The device structure is segmented into bottom device sub-stack and top device sub-stack, allowing independent processing of each stack. The top device sub-stack can be selectively removed to create non-stacked devices with pass gate functionality while preserving bottom device sub-stacks that maintain common gate functionality, thus resolving the contradiction between area efficiency and functional versatility
Solution Approach 2:
Different regions of the substrate are assigned different device configurations: some regions maintain stacked CFET structure for area efficiency, while other regions have top device sub-stacks removed to provide pass gate functionality. This local differentiation allows both common gate and pass gate functions to coexist on the same substrate
2Adaptability or versatility
If top device channel layers are removed to form non-stacked devices, then pass gate functionality is enabled, but manufacturing complexity increases
Solution Approach 1:
The sacrificial gate structure is formed early in the manufacturing process, extending across both bottom and top device sub-stacks. This preliminary structure serves as a template for subsequent selective removal of top device sub-stacks, simplifying the overall manufacturing process by establishing the device configuration pattern before complex processing steps
Solution Approach 2:
The sacrificial gate structure acts as an intermediary element that facilitates the selective removal process. By forming openings in the sacrificial gate structure, the top device sub-stacks can be selectively accessed and removed without affecting bottom device sub-stacks, thereby enabling pass gate functionality while maintaining process control
3Adaptability or versatility
If selective removal of top device sub-stack is performed, then non-stacked device formation is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The sacrificial gate structure serves as a protective intermediary that shields bottom device sub-stacks during the etching process. Openings are formed in the sacrificial gate structure to expose only the top device sub-stacks for removal, while the remaining sacrificial gate material protects the bottom devices, thereby reducing the precision requirements for selective etching
Solution Approach 2:
The sacrificial gate structure is a temporary, disposable element formed specifically to enable selective removal of top device sub-stacks. After serving its protective and guiding function during manufacturing, it is removed along with the top device sub-stacks, simplifying the overall process by using a consumable structure rather than requiring high-precision permanent masking
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the reliable and efficient fabrication of non-stacked transistor devices, such as pass gates, by selectively removing the top device channel layers, thereby preventing active device formation and allowing for area-selective formation of non-stacked devices while preserving the bottom channel layers, enhancing the functionality of integrated circuits.
Implementation Method 1
forming an opening exposing the top device sub-stack, wherein forming the opening comprises etching the sacrificial gate structure; forming a cut through the top device sub-stack by etching back the top device sub-stack from the opening
Data Source
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AI summary
The disclosure relates to a method for forming a semiconductor device, comprising: forming a device structure (400) on a substrate (102), the device structure comprising: a device layer stack comprising a bottom device sub-stack comprising at least one bottom channel layer (124), and a top device sub-stack comprising at least one top channel layer, a sacrificial gate structure extending across the device layer stack, and bottom source/drain structures (126a, 126b) on opposite ends of the at least one bottom channel layer; forming an opening exposing the top device sub-stack, wherein forming the opening comprises etching the sacrificial gate structure; forming a cut through the top device sub-stack by etching back the top device sub-stack from the opening, wherein the etching extends through each of the at least one top channel layer and is stopped over the bottom device sub-stack; and subsequent to forming the cut, forming a functional gate stack (480) on the at least one bottom channel layer.