CFET Superlattice Isolation Layer for Mobility and Dopant Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving enhanced performance due to limitations in charge carrier mobility and dopant diffusion, which affect device efficiency and reliability.
Innovation Solution
The implementation of a semiconductor device with a superlattice isolation layer, comprising stacked groups of layers with base semiconductor monolayers and non-semiconductor monolayers constrained within the crystal lattice, to enhance charge carrier mobility and reduce dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor structures are used, then manufacturing is simpler, but charge carrier mobility is limited
Solution Approach 1:
The patent employs a composite superlattice structure comprising alternating layers of silicon and silicon-germanium materials. This composite architecture enables simultaneous achievement of high charge carrier mobility through strain engineering and effective dopant diffusion barriers, resolving the contradiction between performance enhancement and structural complexity
Solution Approach 2:
The isolation layer is segmented into multiple thin monolayers arranged in a superlattice configuration. This segmentation allows each layer to contribute specific functions - silicon layers provide structural integrity and carrier transport pathways, while silicon-germanium layers provide strain-induced mobility enhancement and diffusion blocking, collectively improving charge carrier mobility without excessive complexity
2Reliability
If dopant diffusion is allowed for device fabrication, then manufacturing is easier, but device reliability deteriorates due to dopant contamination
Solution Approach 1:
The superlattice isolation layer acts as an intermediary barrier between n-type and p-type doped regions. The alternating silicon and silicon-germanium monolayers create a diffusion barrier that prevents dopant contamination while maintaining structural continuity and electrical isolation, thereby enhancing device reliability without significantly complicating the fabrication process
Solution Approach 2:
The patent utilizes parameter changes in material composition - specifically varying the germanium content in silicon-germanium layers - to optimize the balance between dopant diffusion barrier properties and structural integrity. By adjusting compositional parameters, the isolation layer effectively blocks dopant diffusion while remaining compatible with standard fabrication processes
3Speed
If material layers are added to enhance mobility, then charge carrier mobility improves, but manufacturing precision requirements increase
Solution Approach 1:
The superlattice structure employs partial action by using a limited number of alternating monolayers (typically 3-7 periods) rather than excessive thickness. Each monolayer is designed to provide just sufficient strain and diffusion barrier properties, achieving the required mobility enhancement while keeping the total layer thickness manageable and precision requirements within practical manufacturing capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The superlattice structure improves charge carrier mobility by reducing effective mass and scattering, while also acting as a barrier to dopant diffusion, thereby enhancing device performance and reliability.
Implementation Method 1
The superlattice structure improves charge carrier mobility by reducing effective mass and scattering
Implementation Method 2
The superlattice structure improves charge carrier mobility by reducing effective mass and scattering, while also acting as a barrier to dopant diffusion
Data Source
AI summary
A semiconductor device may include a plurality of complimentary field effect transistors (CFETs). Each CFET may include an n-channel field effect transistor (NFET) and a p-channel field effect transistor (PFET) stacked in vertical relation, with each of the NFET and PFET including spaced apart source and drain regions defining respective channels therebetween. Each CFET may further include a gate overlying both of the channels, and at least one isolation layer between the NFET and the PFET. The at least one isolation layer may include a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.